From patchwork Wed Oct 21 02:36:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 287367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF7C5C388F9 for ; Wed, 21 Oct 2020 02:36:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 67EA222200 for ; Wed, 21 Oct 2020 02:36:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2439989AbgJUCgV (ORCPT ); Tue, 20 Oct 2020 22:36:21 -0400 Received: from mga07.intel.com ([134.134.136.100]:24514 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2439986AbgJUCgV (ORCPT ); Tue, 20 Oct 2020 22:36:21 -0400 IronPort-SDR: bV4FcmrRB5O3hOFGkUUQAAD3xp5vZ22ewau9e64XEUOi9ANl+xLm65V5bl88KZepJJJLddr7y1 HFhAyJ9g/JTA== X-IronPort-AV: E=McAfee;i="6000,8403,9780"; a="231498474" X-IronPort-AV: E=Sophos;i="5.77,399,1596524400"; d="scan'208";a="231498474" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2020 19:36:20 -0700 IronPort-SDR: 2koM1jwv6J1QNXjjrCXuTE+67Yq2TnAyG7+5X6AO0EcTN/eOO7uCJk/xPnLZbhaIj2GId+8Rdt DlKmed5UEISw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,399,1596524400"; d="scan'208";a="466136946" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2020 19:36:17 -0700 From: "Ramuthevar,Vadivel MuruganX" To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, "Ramuthevar,Vadivel MuruganX" Subject: [PATCH v2 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Date: Wed, 21 Oct 2020 10:36:09 +0800 Message-Id: <20201021023615.48982-1-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add QSPI controller support for Intel LGM SoC. Note from Vignesh(mtd subsystem maintainer): This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX that intended to move cadence-quadspi driver to spi-mem framework Those patches were trying to accomplish too many things in a single set of patches and need to split into smaller patches. This is reduced version of above series. Changes that are intended to make migration easy are split into separate patches. Patches 1 to 3 drop features that cannot be supported under spi-mem at the moment (backward compatibility is maintained). Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to spi-mem and patch 7 moves the driver to drivers/spi folder. I have tested both INDAC mode (used by non TI platforms like Altera SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs. Patches to move move bindings over to "Documentation/devicetree/bindings/spi/" directory and also conversion of bindig doc to YAML will be posted separately. Support for Intel platform would follow that. Reference: https://lkml.org/lkml/2020/6/1/50 --- v2: - Rob's review comments update for dt-bindings - add 'oneOf' for compatible selection - drop un-neccessary descriptions - add the cdns,is-decoded-cs and cdns,rclk-en properties as schema - remove 'allOf' in not required place - add AdditionalProperties false - add minItems/maxItems for qspi reset attributes resend-v1: - As per Mark's suggestion , reorder the patch series 1-3 driver support patches, series 4-6 dt-bindings patches. v1: - initial version Ramuthevar Vadivel Murugan (6): spi: cadence-quadspi: Disable the DAC for Intel LGM SoC spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml dt-bindings: spi: Add compatible for Intel LGM SoC dt-bindings: spi: Add compatible for Intel LGM SoC .../devicetree/bindings/mtd/cadence-quadspi.txt | 67 --------- .../devicetree/bindings/spi/cadence-quadspi.yaml | 149 +++++++++++++++++++++ drivers/spi/spi-cadence-quadspi.c | 26 ++++ 3 files changed, 175 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml