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Fri, 29 Sep 2023 17:40:55 +0000 From: Matthew Howell To: "gregkh@linuxfoundation.org" CC: "linux-serial@vger.kernel.org" , Darren Beeson , "andriy.shevchenko@intel.com" , "ilpo.jarvinen@linux.intel.com" , "eff.baldwin@sealevel.com" , James Olson , Ryan Wenglarz Subject: [PATCH V9 2/2] serial: exar: Add RS-485 support for Sealevel XR17V35X based cards Thread-Topic: [PATCH V9 2/2] serial: exar: Add RS-485 support for Sealevel XR17V35X based cards Thread-Index: AQHZ8vwZPu3UINjLFE+mWTp0CWmRiw== Date: Fri, 29 Sep 2023 17:40:55 +0000 Message-ID: <4b8ad8ab6728742464c4e048fdeecb2b40522aef.camel@sealevel.com> References: <8ffa2f583ff142c3b0eb6cf51a7c9cef5dbfd320.camel@sealevel.com> In-Reply-To: <8ffa2f583ff142c3b0eb6cf51a7c9cef5dbfd320.camel@sealevel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Evolution 3.44.4-0ubuntu2 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=sealevel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: BY3PR05MB8419:EE_|PH8PR05MB9362:EE_ x-ms-office365-filtering-correlation-id: bb07e7d6-c13e-4606-e70e-08dbc1133c0d x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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This patch implements DTR Auto-RS485 on Sealevel cards. Signed-off-by: Matthew Howell Reviewed-by: Andy Shevchenko --- V8->V9 Changed implementation to use pci_xr17v35x_setup() instead of creating separate startup functions. diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c index 3886f78ecbbf..f4a467d5b6aa 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -78,6 +78,9 @@ #define UART_EXAR_RS485_DLY(x) ((x) << 4) +#define UART_EXAR_DLD 0x02 /* Divisor Fractional */ +#define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */ + /* * IOT2040 MPIO wiring semantics: * @@ -439,6 +442,44 @@ static int generic_rs485_config(struct uart_port *port, struct ktermios *termios return 0; } +static int sealevel_rs485_config(struct uart_port *port, struct ktermios *termios, + struct serial_rs485 *rs485) +{ + u8 __iomem *p = port->membase; + u8 old_lcr; + u8 efr; + u8 dld; + int ret; + + ret = generic_rs485_config(port, termios, rs485); + if (ret) + return ret; + + if (rs485->flags & SER_RS485_ENABLED) { + old_lcr = readb(p + UART_LCR); + + /* Set EFR[4]=1 to enable enhanced feature registers */ + efr = readb(p + UART_XR_EFR); + efr |= UART_EFR_ECB; + writeb(efr, p + UART_XR_EFR); + + /* Set MCR to use DTR as Auto-RS485 Enable signal */ + writeb(UART_MCR_OUT1, p + UART_MCR); + + /* Set LCR[7]=1 to enable access to DLD register */ + writeb(old_lcr | UART_LCR_DLAB, p + UART_LCR); + + /* Set DLD[7]=1 for inverted RS485 Enable logic */ + dld = readb(p + UART_EXAR_DLD); + dld |= UART_EXAR_DLD_485_POLARITY; + writeb(dld, p + UART_EXAR_DLD); + + writeb(old_lcr, p + UART_LCR); + } + + return 0; +} + static const struct serial_rs485 generic_rs485_supported = { .flags = SER_RS485_ENABLED, }; @@ -560,6 +601,9 @@ pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev, port->port.rs485_config = platform->rs485_config; port->port.rs485_supported = *(platform->rs485_supported); + if (pcidev->subsystem_vendor == PCI_VENDOR_ID_SEALEVEL) + port->port.rs485_config = sealevel_rs485_config; + /* * Setup the UART clock for the devices on expansion slot to * half the clock speed of the main chip (which is 125MHz)