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Wed, 24 Apr 2024 06:30:02 -0500 From: Manikanta Guntupalli To: , , , , , , , , , , , , , , , , , , CC: , , , Manikanta Guntupalli Subject: [PATCH V2 3/3] tty: serial: uartps: Add support for uartps controller reset Date: Wed, 24 Apr 2024 16:59:33 +0530 Message-ID: <20240424112933.3528590-4-manikanta.guntupalli@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240424112933.3528590-1-manikanta.guntupalli@amd.com> References: <20240424112933.3528590-1-manikanta.guntupalli@amd.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DA:EE_|DS7PR12MB5743:EE_ X-MS-Office365-Filtering-Correlation-Id: 8276e823-117a-4945-bbdc-08dc6451e6e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|7416005|36860700004|376005|82310400014|1800799015|921011; X-Microsoft-Antispam-Message-Info: acIkmBbgM2OmqhAUMJv/QiEtfdb9l6heP5ehE+GKzzbpyoKecp1dqm8peivvCU2CXtsOT+SDJoFmIekGBXIAYc9IHC9WZbIDBCvvdYpYL/H7u53dermIzfOl01a3QL5T/2syzDg4zxvLHG3qPFW/I6bPJ95ffPuh0gqlF/xDHucW3Q4f3/TC72EmiLUM38LvF+00Xy7xOfAhTXCYAljIV1XxIQy2fogfozUIDc0bqEvy2d54KCLCvLL2cjmF+6jcFA83NZFGtm/vHEEI84uKnxbJNIjPSU5dY6Wp5U+gkUwEWFwaYY8eiEYmIZeMpS8+76M8mgJ14s7Mk3+59cyCcJ7/5TSQFKpOwPac3odtGYk2kMwCLKfqaXuNbh2jcTV+6zwEUmBGOTk8QWMYOjogvIsZCa3TLczBlVYF9EKiUEW5KJjLxoEjWf4M5wNZLUSPkTmd33yBfijVdAwHSm0uLe93nY09Kh9YaBP+Ghk3nDcvBJ8BbZzjxez4YJgcxBDWSp3/vrEhwael8gRo3FLQERjo4z9ydvLYydT3W8mXLffqzV6jZPLgyCVsQZzywMy6alcs/Z5LdplCMpCv+GNULgzY7KIHCKUxdxIUt7smRRJvY2esxQ2VQdbgbmQmYyAeuAnrygHGCxJK7KG2jI9zLZjr6/I3EFT05Jp/sEWk88qRpV6u3zcXjT/ytz8TO8TGp3v5QfrPQq3QJkeIjEscm+MZH7mXnIXzyGEbTwQgtpgvv/UTSb1rsx2fZtYEQZ5vpZluVETe7F1s7dRmg60F3wjpBiJQWujtaW/Lz2Oo6eOS1LifaF1nWP1US6y1DMQHjkMEq8566o6EMwkwzq//mL6ZTb2Rms/EMqQb/9i6fr5HBLi8mFRubQIWRHhUTKWrbEp61Fqu/9DMR0xDChmy/xGqUPxy/ZD4HOO+NWd2OpM4psSqrvsawpAPG46c1qqeYN8XolSDFw0a8C2efMeQJn9h0hOr6i+47MIi8vvW6p1sr9SyO1GAN8RntNtxo6P7WjfgZKFW4MRKBTMHmFqsZZBnooOQefW/1oe9XLG8TKejx8TfE6BqGdeT2teS2qs34JhZOM+aS64d1Fa8mVycRmLXCZNVaO4oLg2JADLb+8OfhrrcqyB9olf05f26+ch99xL4BMWhRPdEh0521tQh1TqXtsVEPhfQKk8dQSbuTHdi9nurMQr4EAws2zjvGxnU1jL6g+EUBMuS4gW6nwuXtF+JzyILo70pUyBD7ldyk9HgajJhXwWruAAPP3OLoMSc7I0EERD+ajBz6dHBN2/h4lsSI3vibrIpIEO3udCec0x/hLs9vbf4eKmkBSUUHZhRe8fPKjfNeWn/0JZ2s5L+CbbWxAuPYgOioNE76qTl3L4IlgZk98ChGn6MSiA76N0x X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:ErrorRetry; CAT:NONE; SFS:(13230031)(7416005)(36860700004)(376005)(82310400014)(1800799015)(921011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2024 11:30:10.7799 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8276e823-117a-4945-bbdc-08dc6451e6e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5743 Add support for an optional reset for the uartps controller using the reset driver. If the uartps node contains the "resets" property, then cdns_uart_startup performs uartps controller non-pulse out of reset and reset in exit path. Signed-off-by: Manikanta Guntupalli --- Changes for V2: Remove check for reset_control_deassert, as reset_control_deassert function internally has NULL check --- drivers/tty/serial/xilinx_uartps.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c index de3487206bcb..2acfcea403ce 100644 --- a/drivers/tty/serial/xilinx_uartps.c +++ b/drivers/tty/serial/xilinx_uartps.c @@ -25,6 +25,7 @@ #include #include #include +#include #define CDNS_UART_TTY_NAME "ttyPS" #define CDNS_UART_NAME "xuartps" @@ -198,6 +199,7 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); * @gpiod_rts: Pointer to the gpio descriptor * @rs485_tx_started: RS485 tx state * @tx_timer: Timer for tx + * @rstc: Pointer to the reset control */ struct cdns_uart { struct uart_port *port; @@ -211,6 +213,7 @@ struct cdns_uart { struct gpio_desc *gpiod_rts; bool rs485_tx_started; struct hrtimer tx_timer; + struct reset_control *rstc; }; struct cdns_platform_data { u32 quirks; @@ -948,6 +951,10 @@ static int cdns_uart_startup(struct uart_port *port) is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; + ret = reset_control_deassert(cdns_uart->rstc); + if (ret) + return ret; + uart_port_lock_irqsave(port, &flags); /* Disable the TX and RX */ @@ -1721,6 +1728,13 @@ static int cdns_uart_probe(struct platform_device *pdev) dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); } + cdns_uart_data->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); + if (IS_ERR(cdns_uart_data->rstc)) { + rc = PTR_ERR(cdns_uart_data->rstc); + dev_err_probe(&pdev->dev, rc, "Cannot get UART reset\n"); + goto err_out_unregister_driver; + } + rc = clk_prepare_enable(cdns_uart_data->pclk); if (rc) { dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); @@ -1881,6 +1895,7 @@ static void cdns_uart_remove(struct platform_device *pdev) if (console_port == port) console_port = NULL; #endif + reset_control_assert(cdns_uart_data->rstc); if (!--instances) uart_unregister_driver(cdns_uart_data->cdns_uart_driver);