From patchwork Mon Apr 1 10:10:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 785074 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70C6E134C8; Mon, 1 Apr 2024 10:10:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711966255; cv=none; b=MGew8ZSPqL1nYViZPxY8at66bH2vd4jEj8RXmNy8EBXyztCeu1hkJkTDLjGQR15umcHr8e1svyYesySRGIwuaWdQWZ8zOSfCGyuOT4pymEUqD7Sm4YOCpXiyWq/M6u17irzfx22cdJXgA554c58MO0kEjCq3QXQCN1AhUvU411w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711966255; c=relaxed/simple; bh=2JElwhxMTZ+Lyru/NySatkrI9lsl5FsVk/jVdzEHjgU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hOjmBOMdMcsbm4VqNCXF0IYoHLYQa8yUvG3yRByAvrJjSKp5YC7p5cwLq7xU1IUl/IZ4WkKmkPjL502pGnSI2uA27xC/dg48dWHqm6mMdnGIhWhd2MXMdH2zGSsmWoU6k+OzVvHQqtD11uZcbT5kzmrp8lrSSDvevODiNb8gJIw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AEGvKkRe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AEGvKkRe" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0620DC433B2; Mon, 1 Apr 2024 10:10:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711966255; bh=2JElwhxMTZ+Lyru/NySatkrI9lsl5FsVk/jVdzEHjgU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=AEGvKkRejq2SMOK+FKxUN152QhuUmoKSgMd4gi6WZQCtkRdr5U7K+h31hkI1Kvok8 AHY2Q7OpAp5mlHkc+23AYKuNaKkfoM5+uDSI40LfbuCRV6EVw3KKZh1YICRpZVa6FA 2Skmn28fOeudHWmH3vHIhIdO3e7gsNwIsJrZH0oFaEqoLj9VnG9sKy4ZDxM8cGlxcw NbSqpygelJqn3YEqAqZIzhVXt91FYyxK6QS+uO153uLcj0M6YT69fpXRSmw3Yiwpv2 CI2Z9yquYotl+MCxG92CVB/PlDDIXZ+ZtsW2eC2SmMhHTy4VRmp/HPktPOcAo2tKem cX7tA1mkvXklg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF328CD1292; Mon, 1 Apr 2024 10:10:54 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Mon, 01 Apr 2024 18:10:52 +0800 Subject: [PATCH v3 4/5] arm64: dts: add support for A4 based Amlogic BA400 Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240401-basic_dt-v3-4-cb29ae1c16da@amlogic.com> References: <20240401-basic_dt-v3-0-cb29ae1c16da@amlogic.com> In-Reply-To: <20240401-basic_dt-v3-0-cb29ae1c16da@amlogic.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Martin Blumenstingl , Jerome Brunet , Kevin Hilman , Greg Kroah-Hartman , Jiri Slaby Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-serial@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1711966253; l=5466; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=RfLd574Wp3hwxF/pWxflQftrTi/f96C/bPSUXXZxmuU=; b=y7iWoA3HnB5R9vMExVG8RSqBloO7jAcKNWCMoX0siVo2I01qYN3/Gzzf9K2JyvqFaULwstrHM eZ3EBAxQzXkD8+OphzS92wuZ8ZZSW3Ja1xE/iovJJ+ODaHZvTWLLakH X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Amlogic A4 is an application processor designed for smart audio and IoT applications. Add basic support for the A4 based Amlogic BA400 board, which describes the following components: CPU, GIC, IRQ, Timer and UART. These are capable of booting up into the serial console. Signed-off-by: Xianwei Zhao Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts | 42 ++++++++++++++ arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi | 66 ++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 40 +++++++++++++ 4 files changed, 149 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 1ab160bf928a..9a50ec11bb8d 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts new file mode 100644 index 000000000000..ad3127e695d9 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "amlogic-a4.dtsi" + +/ { + model = "Amlogic A113L2 ba400 Development Board"; + compatible = "amlogic,ba400", "amlogic,a4"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_b; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 10 MiB reserved for ARM Trusted Firmware */ + secmon_reserved: secmon@5000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x05000000 0x0 0xa00000>; + no-map; + }; + }; +}; + +&uart_b { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi new file mode 100644 index 000000000000..b6106ad4a072 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +/ { + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = ; + }; + + apb: bus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_b: serial@7a000 { + compatible = "amlogic,a4-uart", + "amlogic,meson-s4-uart"; + reg = <0x0 0x7a000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi new file mode 100644 index 000000000000..73ca1d7eed81 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +#include "amlogic-a4-common.dtsi" +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; +};