| Message ID | 20231201160925.3136868-16-peter.griffin@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board | expand |
On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > The WDT uses the CPU core signal DBGACK to determine whether the SoC > is running in debug mode or not. If the DBGACK signal is asserted and > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > (disabled). > > Presence of the DBGACK_MASK bit is determined by adding a new > QUIRK_HAS_DBGACK_BIT quirk. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/watchdog/s3c2410_wdt.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > index 0b4bd883ff28..39f3489e41d6 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -34,9 +34,10 @@ > > #define S3C2410_WTCNT_MAXCNT 0xffff > > -#define S3C2410_WTCON_RSTEN (1 << 0) > -#define S3C2410_WTCON_INTEN (1 << 2) > -#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_RSTEN (1 << 0) > +#define S3C2410_WTCON_INTEN (1 << 2) > +#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) Suggest using BIT() macro. Btw, checkpatch with --strict option suggests it too :) > > #define S3C2410_WTCON_DIV16 (0 << 3) > #define S3C2410_WTCON_DIV32 (1 << 3) > @@ -100,12 +101,17 @@ > * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) > * with "watchdog counter enable" bit. That bit should be set to make watchdog > * counter running. > + * > + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the > + * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. > + * Debug mode is determined by the DBGACK CPU signal. > */ > #define QUIRK_HAS_WTCLRINT_REG (1 << 0) > #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) > #define QUIRK_HAS_PMU_RST_STAT (1 << 2) > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > #define QUIRK_HAS_PMU_CNT_EN (1 << 4) > +#define QUIRK_HAS_DBGACK_BIT (1 << 5) > > /* These quirks require that we have a PMU register map */ > #define QUIRKS_HAVE_PMUREG \ > @@ -375,6 +381,19 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > return 0; > } > > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) > +{ > + unsigned long wtcon; > + > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) > + return; > + > + /* disable watchdog outputs if CPU is in debug mode */ Double whitespace in the comment. Also, I'd move this comment up to the function declaration. Other than that: Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > + wtcon = readl(wdt->reg_base + S3C2410_WTCON); > + wtcon |= S3C2410_WTCON_DBGACK_MASK; > + writel(wtcon, wdt->reg_base + S3C2410_WTCON); > +} > + > static int s3c2410wdt_keepalive(struct watchdog_device *wdd) > { > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); > @@ -700,6 +719,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); > wdt->wdt_device.parent = dev; > > + s3c2410wdt_mask_dbgack(wdt); > + > /* > * If "tmr_atboot" param is non-zero, start the watchdog right now. Also > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. > -- > 2.43.0.rc2.451.g8631bc7472-goog >
Hi Sam, On Sat, 2 Dec 2023 at 00:53, Sam Protsenko <semen.protsenko@linaro.org> wrote: > > On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > > > The WDT uses the CPU core signal DBGACK to determine whether the SoC > > is running in debug mode or not. If the DBGACK signal is asserted and > > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > > (disabled). > > > > Presence of the DBGACK_MASK bit is determined by adding a new > > QUIRK_HAS_DBGACK_BIT quirk. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > drivers/watchdog/s3c2410_wdt.c | 27 ++++++++++++++++++++++++--- > > 1 file changed, 24 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > > index 0b4bd883ff28..39f3489e41d6 100644 > > --- a/drivers/watchdog/s3c2410_wdt.c > > +++ b/drivers/watchdog/s3c2410_wdt.c > > @@ -34,9 +34,10 @@ > > > > #define S3C2410_WTCNT_MAXCNT 0xffff > > > > -#define S3C2410_WTCON_RSTEN (1 << 0) > > -#define S3C2410_WTCON_INTEN (1 << 2) > > -#define S3C2410_WTCON_ENABLE (1 << 5) > > +#define S3C2410_WTCON_RSTEN (1 << 0) > > +#define S3C2410_WTCON_INTEN (1 << 2) > > +#define S3C2410_WTCON_ENABLE (1 << 5) > > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) > > Suggest using BIT() macro. Btw, checkpatch with --strict option > suggests it too :) Yes indeed. I was somewhat reluctant to include changes that had nothing to do with the DBGACK feature but I will update to use the BIT macro in v6. > > > > > #define S3C2410_WTCON_DIV16 (0 << 3) > > #define S3C2410_WTCON_DIV32 (1 << 3) > > @@ -100,12 +101,17 @@ > > * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) > > * with "watchdog counter enable" bit. That bit should be set to make watchdog > > * counter running. > > + * > > + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the > > + * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. > > + * Debug mode is determined by the DBGACK CPU signal. > > */ > > #define QUIRK_HAS_WTCLRINT_REG (1 << 0) > > #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) > > #define QUIRK_HAS_PMU_RST_STAT (1 << 2) > > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > > #define QUIRK_HAS_PMU_CNT_EN (1 << 4) > > +#define QUIRK_HAS_DBGACK_BIT (1 << 5) > > > > /* These quirks require that we have a PMU register map */ > > #define QUIRKS_HAVE_PMUREG \ > > @@ -375,6 +381,19 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > > return 0; > > } > > > > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) > > +{ > > + unsigned long wtcon; > > + > > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) > > + return; > > + > > + /* disable watchdog outputs if CPU is in debug mode */ > > Double whitespace in the comment. Also, I'd move this comment up to > the function declaration. Will fix > > Other than that: > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Thanks, Peter > > > + wtcon = readl(wdt->reg_base + S3C2410_WTCON); > > + wtcon |= S3C2410_WTCON_DBGACK_MASK; > > + writel(wtcon, wdt->reg_base + S3C2410_WTCON); > > +} > > + > > static int s3c2410wdt_keepalive(struct watchdog_device *wdd) > > { > > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); > > @@ -700,6 +719,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); > > wdt->wdt_device.parent = dev; > > > > + s3c2410wdt_mask_dbgack(wdt); > > + > > /* > > * If "tmr_atboot" param is non-zero, start the watchdog right now. Also > > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. > > -- > > 2.43.0.rc2.451.g8631bc7472-goog > >
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 0b4bd883ff28..39f3489e41d6 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -34,9 +34,10 @@ #define S3C2410_WTCNT_MAXCNT 0xffff -#define S3C2410_WTCON_RSTEN (1 << 0) -#define S3C2410_WTCON_INTEN (1 << 2) -#define S3C2410_WTCON_ENABLE (1 << 5) +#define S3C2410_WTCON_RSTEN (1 << 0) +#define S3C2410_WTCON_INTEN (1 << 2) +#define S3C2410_WTCON_ENABLE (1 << 5) +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) #define S3C2410_WTCON_DIV16 (0 << 3) #define S3C2410_WTCON_DIV32 (1 << 3) @@ -100,12 +101,17 @@ * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) * with "watchdog counter enable" bit. That bit should be set to make watchdog * counter running. + * + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the + * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. + * Debug mode is determined by the DBGACK CPU signal. */ #define QUIRK_HAS_WTCLRINT_REG (1 << 0) #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) #define QUIRK_HAS_PMU_RST_STAT (1 << 2) #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) #define QUIRK_HAS_PMU_CNT_EN (1 << 4) +#define QUIRK_HAS_DBGACK_BIT (1 << 5) /* These quirks require that we have a PMU register map */ #define QUIRKS_HAVE_PMUREG \ @@ -375,6 +381,19 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) return 0; } +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) +{ + unsigned long wtcon; + + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) + return; + + /* disable watchdog outputs if CPU is in debug mode */ + wtcon = readl(wdt->reg_base + S3C2410_WTCON); + wtcon |= S3C2410_WTCON_DBGACK_MASK; + writel(wtcon, wdt->reg_base + S3C2410_WTCON); +} + static int s3c2410wdt_keepalive(struct watchdog_device *wdd) { struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); @@ -700,6 +719,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); wdt->wdt_device.parent = dev; + s3c2410wdt_mask_dbgack(wdt); + /* * If "tmr_atboot" param is non-zero, start the watchdog right now. Also * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
The WDT uses the CPU core signal DBGACK to determine whether the SoC is running in debug mode or not. If the DBGACK signal is asserted and DBGACK_MASK bit is enabled, then WDT output and interrupt is masked (disabled). Presence of the DBGACK_MASK bit is determined by adding a new QUIRK_HAS_DBGACK_BIT quirk. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> --- drivers/watchdog/s3c2410_wdt.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-)