From patchwork Thu May 18 15:22:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 683866 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47047C77B7A for ; Thu, 18 May 2023 15:34:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231895AbjERPev (ORCPT ); Thu, 18 May 2023 11:34:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231883AbjERPeY (ORCPT ); Thu, 18 May 2023 11:34:24 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DE70E43; Thu, 18 May 2023 08:34:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9FF5A64FE8; Thu, 18 May 2023 15:34:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 96ECAC433A1; Thu, 18 May 2023 15:34:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684424056; bh=mtrxumyq0ZRmNVTAnw5KH+BUNijjTRh/kWJxJPGHbDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SGbIB8w46x8K+bS/h1IrsArBKnSUDQbJusl259FltuEAMHQqWk3iv737Cdkla9WfR Y+5uxpZ02rQObZCuaFvWsEIiinWanCxu6jg/3qHNmGFoo5Z1x0h5lD4WeK690TkIla LncuBttq0p4NHcU2Qhdsbkb54XtzwUONOw2RtkU1MH9/12vAkY5lOZi/3i4OV+Rr/J Sy31Qa+4U1sa8gUSvbBYGwVjh43c88H8+MX8SuN/KkMa9aLTAu6L0AxiOblcs8eT9w Az6U5RvDBNn8sozrIWJwkPb70SXVvfDtjyFGVV/z2kZlIOffPPrufHk6WS4Q/th5E1 9QO4d4mtc/I6g== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Greg Kroah-Hartman , Jiri Slaby Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, Conor Dooley , Palmer Dabbelt Subject: [PATCH v4 05/10] riscv: add the Bouffalolab SoC family Kconfig option Date: Thu, 18 May 2023 23:22:39 +0800 Message-Id: <20230518152244.2178-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518152244.2178-1-jszhang@kernel.org> References: <20230518152244.2178-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and LP. The D0 is 64bit RISC-V GC compatible, so can run linux. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..33220b5144bb 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,10 @@ menu "SoC selection" +config ARCH_BOUFFALOLAB + bool "Bouffalolab SoCs" + help + This enables support for Bouffalolab SoC platforms. + config ARCH_MICROCHIP_POLARFIRE def_bool SOC_MICROCHIP_POLARFIRE