From patchwork Sun May 14 16:56:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 682306 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60C23C7EE23 for ; Sun, 14 May 2023 17:08:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237845AbjENRIw (ORCPT ); Sun, 14 May 2023 13:08:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235813AbjENRI2 (ORCPT ); Sun, 14 May 2023 13:08:28 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CE973C07; Sun, 14 May 2023 10:08:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A2D2260A48; Sun, 14 May 2023 17:08:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 99D69C433A0; Sun, 14 May 2023 17:08:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684084101; bh=mtrxumyq0ZRmNVTAnw5KH+BUNijjTRh/kWJxJPGHbDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fvXP+Y7I3i3ihYdVkNewCBLQsD/O0zHS0lGhnogvEMO8oiDFPpC6/t+lxpjKhzHPW oH70PSK2jM0zLINBqMLjX/u9btWauAIQ7HNe1V37K+2vR7GMdAP5BcvcMiF8LmKhTv V4Ar+Z1o6kkaGQWnr9Z1pooXcsYN4aN05qxjGQSDc3jGpRvOG/+xkg2n3uZPFgFaH7 EcrSkkp4qR6O3IvHVjGiqRYujd5+AaZ4mC9cA8rzmtAAFHyIJnY4flWI1DFZvKy9IH YsO0dXae8EjHf3WQmssR5WKI8zcsrnI9ScUQsMRva+IjkHnOoeWcM/Z+byHqX06atA e3WEbiCuvbw3Q== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Greg Kroah-Hartman , Jiri Slaby Cc: Samuel Holland , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, Conor Dooley , Palmer Dabbelt Subject: [PATCH v3 05/10] riscv: add the Bouffalolab SoC family Kconfig option Date: Mon, 15 May 2023 00:56:46 +0800 Message-Id: <20230514165651.2199-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230514165651.2199-1-jszhang@kernel.org> References: <20230514165651.2199-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and LP. The D0 is 64bit RISC-V GC compatible, so can run linux. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..33220b5144bb 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,10 @@ menu "SoC selection" +config ARCH_BOUFFALOLAB + bool "Bouffalolab SoCs" + help + This enables support for Bouffalolab SoC platforms. + config ARCH_MICROCHIP_POLARFIRE def_bool SOC_MICROCHIP_POLARFIRE