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Wed, 20 Jul 2022 07:26:18 -0700 Envelope-to: git@xilinx.com, linux-serial@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org, robh+dt@kernel.org, devicetree@vger.kernel.org Received: from [10.140.6.59] (port=55844 helo=xhdshubhraj40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1oEAeX-0000jg-LR; Wed, 20 Jul 2022 07:26:18 -0700 From: Shubhrajyoti Datta To: CC: , , , , , Subject: [PATCH v2 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart' Date: Wed, 20 Jul 2022 19:56:11 +0530 Message-ID: <20220720142612.19779-2-shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220720142612.19779-1-shubhrajyoti.datta@xilinx.com> References: <20220720142612.19779-1-shubhrajyoti.datta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 72586925-0de9-4c2f-9e35-08da6a5bd060 X-MS-TrafficTypeDiagnostic: DM6PR02MB5211:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(396003)(136003)(376002)(39860400002)(346002)(40470700004)(36840700001)(46966006)(70586007)(8676002)(7696005)(4326008)(70206006)(8936002)(186003)(82310400005)(426003)(47076005)(336012)(6916009)(40480700001)(44832011)(83380400001)(356005)(82740400003)(54906003)(40460700003)(316002)(2616005)(478600001)(36756003)(5660300002)(6666004)(26005)(9786002)(36860700001)(2906002)(7636003)(41300700001)(1076003)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2022 14:26:19.5813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72586925-0de9-4c2f-9e35-08da6a5bd060 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0060.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5211 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org The Xilinx Versal board uses the arm,pl011 ip. However the axi port that it is connected to has a limitation that it allows only 32-bit accesses. So to differentiate we add a compatible. Add support for Uart used in Xilinx Versal SOCs as a platform device. Signed-off-by: Shubhrajyoti Datta Signed-off-by: Raviteja Narayanam --- Documentation/devicetree/bindings/serial/pl011.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml index d8aed84abcd3..bf094ab93086 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -24,9 +24,13 @@ select: properties: compatible: - items: - - const: arm,pl011 - - const: arm,primecell + oneOf: + - items: + - const: arm,pl011 + - const: arm,primecell + - items: + - const: arm,pl011 + - const: arm,xlnx-uart # xilinx uart as platform device reg: maxItems: 1