From patchwork Thu Jun 30 10:05:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 586752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B299C433EF for ; Thu, 30 Jun 2022 10:06:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234844AbiF3KGe (ORCPT ); Thu, 30 Jun 2022 06:06:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234754AbiF3KGU (ORCPT ); Thu, 30 Jun 2022 06:06:20 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B9A244746; Thu, 30 Jun 2022 03:06:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656583562; x=1688119562; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=aArJ+/tttqsgdUdRKLHM2+KGCl1I1CRCDeLBubWfQwE=; b=PNBZq6mfFWoqxaaECS3VEiO0KkpuyCXqzm5ALCfjpjhy4OY0OIPq1s6e ZFDFu6/j+9ZUOFneOTXYW6NA4mrPctVPj4ivRxMgcbHBKHCBQWKVaUDY3 78CMJSnMbV1qkha+yNV2QAKy3xvlSKif60F5/leAaIyahgGmhJ82T8hzU Xr8h6y7niYiawspT1yPezh0a+DyLR78p0Nn3aCGT3r2vmGxboAlY2FhsB YYHPK1Gm2XYYw1yYNIRYlKbZS72s6my6Zp/Ua2Y06kNuPoZGOLqcqRkq8 DIajF5/jgscf+SNcnL+XFh+R7TlRGsOiJ1PzDE7zNuZjZhW/hVqR6Wra6 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10393"; a="282340073" X-IronPort-AV: E=Sophos;i="5.92,233,1650956400"; d="scan'208";a="282340073" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2022 03:05:49 -0700 X-IronPort-AV: E=Sophos;i="5.92,233,1650956400"; d="scan'208";a="647826781" Received: from emontau-mobl2.ger.corp.intel.com (HELO ijarvine-MOBL2.ger.corp.intel.com) ([10.249.42.178]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2022 03:05:48 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Andy Shevchenko , Greg Kroah-Hartman , Jiri Slaby , linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/1] 8250_dwlib: Convert bitops to newer form Date: Thu, 30 Jun 2022 13:05:36 +0300 Message-Id: <20220630100536.41329-1-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Instead of open-coding, use BIT(), GENMASK(), and FIELD_GET() helpers. Signed-off-by: Ilpo Järvinen --- drivers/tty/serial/8250/8250_dwlib.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c index da330ef46446..a8bbed74ea70 100644 --- a/drivers/tty/serial/8250/8250_dwlib.c +++ b/drivers/tty/serial/8250/8250_dwlib.c @@ -46,21 +46,21 @@ #define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) /* Component Parameter Register bits */ -#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) -#define DW_UART_CPR_AFCE_MODE (1 << 4) -#define DW_UART_CPR_THRE_MODE (1 << 5) -#define DW_UART_CPR_SIR_MODE (1 << 6) -#define DW_UART_CPR_SIR_LP_MODE (1 << 7) -#define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) -#define DW_UART_CPR_FIFO_ACCESS (1 << 9) -#define DW_UART_CPR_FIFO_STAT (1 << 10) -#define DW_UART_CPR_SHADOW (1 << 11) -#define DW_UART_CPR_ENCODED_PARMS (1 << 12) -#define DW_UART_CPR_DMA_EXTRA (1 << 13) -#define DW_UART_CPR_FIFO_MODE (0xff << 16) +#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) +#define DW_UART_CPR_AFCE_MODE BIT(4) +#define DW_UART_CPR_THRE_MODE BIT(5) +#define DW_UART_CPR_SIR_MODE BIT(6) +#define DW_UART_CPR_SIR_LP_MODE BIT(7) +#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) +#define DW_UART_CPR_FIFO_ACCESS BIT(9) +#define DW_UART_CPR_FIFO_STAT BIT(10) +#define DW_UART_CPR_SHADOW BIT(11) +#define DW_UART_CPR_ENCODED_PARMS BIT(12) +#define DW_UART_CPR_DMA_EXTRA BIT(13) +#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) /* Helper for FIFO size calculation */ -#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) +#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) /* * divisor = div(I) + div(F)