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Ivanov" , "Lee, Chun-Yi" , Chester Lin Subject: [PATCH v2 4/8] arm64: dts: add NXP S32G2 support Date: Wed, 8 Sep 2021 14:45:24 +0800 Message-ID: <20210908064528.922-5-clin@suse.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210908064528.922-1-clin@suse.com> References: <20210908064528.922-1-clin@suse.com> X-ClientProxiedBy: PR0P264CA0107.FRAP264.PROD.OUTLOOK.COM (2603:10a6:100:19::23) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost (36.224.129.215) by PR0P264CA0107.FRAP264.PROD.OUTLOOK.COM (2603:10a6:100:19::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.14 via Frontend Transport; Wed, 8 Sep 2021 06:46:28 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 25b56223-75a8-46ff-2ab5-08d972946311 X-MS-TrafficTypeDiagnostic: VI1PR04MB4000: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: a/vgs5kr8u7EFKFOdvneHcNk/JOGTMAbIdw6/e8evqlFnRTF4jUaBGV3xe9CMmuxaQFWU00b4xlugqpRZ9daDw4Ao8yriMlhkF1aBpiGrLrB0ydSKz0SgwaIcCIvT706nafRyPs1F2jlXwjWu6UXtPIHj3hfWgUeOYL7oxmdnVl+pUlQMMWVXC5xajTf6GzEAKG85PvPRU0Lu9VD+ocKF5pA+XK1lgRdXI8Yq5me4l4/fP8ijSsqh10m/xNma0+hz8tqDWrqxgUfpkg8RJLkJ9HWUEb8Ct1iFgNkF+kbPnW0ZGyA7ieQw+DU9LA56Yj1/7i1ZsMUiSqxDjGTwfOtxrKK8u+uaboCRXqNhk9k2aFTwuJI1eywGlRglYQMu9O6WwJuD7hBKsXVIZA71cFVug3NBbiqffalfaVfIQAWK5NHK4QNTB2vZQllMhis6zTCk0L/ernQbxGCHWOmJjo+UGFGPfNWfcMGw7rqfPd3HmEdXV+zb/MbqEajsr/LsBiP/+vZ/elFNyr8B6cOUNpu7zc4Yd6t+Xm8c4A3SSIpB/ZwZS0EiN8/4mFgNPjOsM31ZwPXsqxQG7X+FYP1+X6M8K1bELUFpcVCmsuTmGeYl7cZ/jzN0Yz4de7wWtNWvKWlHnGq92VokLT6mtGAU9Q67w== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR0402MB3439.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(396003)(366004)(136003)(376002)(346002)(39860400002)(66946007)(38100700002)(66556008)(66476007)(86362001)(7416002)(478600001)(6636002)(2906002)(8936002)(2616005)(110136005)(186003)(5660300002)(6486002)(54906003)(107886003)(8676002)(36756003)(1076003)(26005)(6496006)(956004)(316002)(4326008)(6666004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: IbbMbfcwZGQf3CaQi5lsvu9a/jxZiUByuyFTluM2AApaM4hvI5ZUCMu0tXR+yJtnWiaAiXG+qsekEBgPGYPEWF6IVqsarZmnIE8pg0GoaNQop4OWU/PPL3jmhPi4NfD9CKt1Muk97Zs8YGqgBZqo+iLeE2ignBJXwX1N1kqYv0dy1W5Z9TNdJvKICcfENb0dPAOHVgN+U6UZGu+ogz+SWnNnQrxs9Lf0+9Lisj0hmpE+sQEMF0vpJ955HnDM6Jw0A2tWHbArqki3oENk79brHNmZORshEVdL+XPK88/pm5WU4Talav81yykxu2lXWGDjDyu6lCT0O82gINNx9+MLNnnnpIrc0IFLlojxb6Vl3DeZQoCzlMAkSFgiKRecEdB/ngMRNYTgekBzKtvVvaMpgdsLRI6u2xFRLTfcgDrBhneN+1DEN6GJ030EhNUgV+IDxJgUzj5ZwWz+yIluQ1rc9yQ0mxamXHuV69rchX7vCYH1uAPCqv5vBFBITbm/13r9DcotnUYrcpBtDO99gfInZfQjP8yltNsPaHXporC8/JGaBIIFdcWDGglD5Er62NXzaBKwzLLQyo5Ymgkv/uR40beujWP6eOJxiKUviYPwjDzMnNtlzT0eHjtTIq+4K26Uz7FxhcElPZ37sof5Ml6Z5SDpav4u3x9fOglopRDwvLY6YOM9XmMA5vYzspcoRmQBYPSEnOft1e0hbvv1n/r8lGYJzHuipPyuNcApFwTQVDXBvQgz0WJxeYGLrVDcGHwf2/I6fEUnsh3pQuov28SWsSeTNOd1PS/NGiSW1KlVaNb2ULvO5o/fhQnrckLPp5KwKVmJ35Dgln/jJaz1p+qzzD0pI3LBWz/bTRaFcatvw1Kt8LtFYJkWs7SKxdAkecFv6zUgamAb6oEvk0F/jmvu5GZdu6a4wsC0u8nPiFVjKpIiSG7AeVj8EX00TfzXc+FG6sIZy+P9rV4lvVxpXrzhAPLjw+jZ1M50zsbuoFIBHHKhd2kARNR6cuigU0pBYze8DhzmRRjyRZnzaBTba86zAqADyXkavAbk5QpZNh4mVRw+mHg4kRGN+0vfYFvpH/BygejiXWODcFl98OdzC46Pgt/0wGKB+hsO98Z8qJ2R/XkLm4Pg7caynU8yGgASX1w6+na5yL3aJMz/vOapeTv3GL+UCOOvwTK9RICwjynBFEtDIWXEho8sb/HykVZ6CuLkg+f/snY8fFaCUYQknhn3eMV8UBtUX7esfOWUoANQ55DIcJRTfU3Wnodjj4R6mn8kFpSmmapoA+5xN60etGrqot6roM6DdA9JFJkE8i8yr3YU8enJ5FwtrmtEx53uIzlW X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 25b56223-75a8-46ff-2ab5-08d972946311 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 06:46:30.5333 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: SvU9SEgeHIijcz9t65SBp4yTHi6Vh87gWYuUneA8IIr2sdf0yDfNJ4RWo4CRUOTD X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4000 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add an initial dtsi file for generic SoC features of NXP S32G2. Signed-off-by: Chester Lin --- Changes in v2: - Add a SoC description. - Add an interrupt-affinity to the pmu node. - Move the psci node into the "/firmware" node. - Remove the redundant properties and white lines. - Remove the wrong interrupt specifier from the gic node. - Specify the range and cell-size of /soc [0 - 4 GiB]. - Correct the reserved size of GICR to 512KiB [0x80000]. arch/arm64/boot/dts/freescale/s32g2.dtsi | 99 ++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi new file mode 100644 index 000000000000..53b18671deec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * NXP S32G2 SoC family + * + * Copyright (c) 2021 SUSE LLC + */ + +#include + +/ { + compatible = "nxp,s32g2"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + firmware { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x80000000>; + + gic: interrupt-controller@50800000 { + compatible = "arm,gic-v3"; + reg = <0x50800000 0x10000>, + <0x50880000 0x80000>, + <0x50400000 0x2000>, + <0x50410000 0x2000>, + <0x50420000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +};