From patchwork Thu Jun 10 13:50:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lino Sanfilippo X-Patchwork-Id: 458241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D87BBC47094 for ; Thu, 10 Jun 2021 13:51:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B81DD613C8 for ; Thu, 10 Jun 2021 13:51:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230289AbhFJNxX (ORCPT ); Thu, 10 Jun 2021 09:53:23 -0400 Received: from mout.gmx.net ([212.227.15.18]:45035 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230322AbhFJNxW (ORCPT ); Thu, 10 Jun 2021 09:53:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1623333079; bh=FhMPsDuNTkIcroGrocTv4Th0r3ifg2AX/Ou/LtkyD9w=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date; b=BiEwTRBehru6TfGJTBvOvDehaU04aZ2JPWlbqgTiNkYiSQZCKw9axNjrAeleXMOYA cyrE6xEwHr568LYnX/0/Enyjr/mck1FR2PHJHW6psEZnGP0smMHTPlCjO2zx/krKqO 3s5F9KUC5S0CSdRs3kJxGc/1DG40TeDwiR4cIMU0= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from Venus.fritz.box ([78.42.220.31]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MrQIv-1lWKLg2EdT-00oaTm; Thu, 10 Jun 2021 15:51:19 +0200 From: Lino Sanfilippo To: gregkh@linuxfoundation.org Cc: linux@armlinux.org.uk, jirislaby@kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Lino Sanfilippo Subject: [PATCH] serial: amba-pl011: add RS485 support Date: Thu, 10 Jun 2021 15:50:04 +0200 Message-Id: <20210610135004.7585-1-LinoSanfilippo@gmx.de> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Provags-ID: V03:K1:SnbNrTGSw/Dk5Z77Um92lL9RApvFqWM9OyYcRkT18i759IWDWHa dXa/Sk0oPoKWsoogaKj3u9dBf1sBpfmcruoNVmSUByJgfl/7dVuP5oNcjute+vjzrl6X22O 9SvfUUSTiOWlX9ec0CrztB3i/2LZexfXRd9jtYoFT4B8nTls/qsuGxpoxnx3DzWAyBkJg1X TX/C/lP5TdSVaLMldm/8Q== X-UI-Out-Filterresults: notjunk:1; V03:K0:9EmTWMNaGhc=:xwR3pbxMImgeBCm9Ug6+y6 zrIC0rlDFhfMtxY16wwLj83SfhMxoNSaQcY1VmUZFGJ0jwOVFI3c0ZHQTSYBMK3xg7dzveG5u JQc2byn40bNSepdeJcmM2+A5ff7KrPddreTCX7Wg29FqlasXQj9fKVZUuowQOUt3uBRGwCQzy INQia0lKCTEyCYvW41nI1OyVvNO7D9rleApmP2xapvbPieMzK6CstPgixF7KP0WTh3XIiqlw+ Fdi7Vk8vQCkI1ABFawEKS1DYVBp3XHl5+dCLGIRVtJbQLbHJ1A8qy2pMclYmnl27jW+jFEphH pFxNDWPM3xTdT9dUvzBBGV0rzOq/C7sxoFiw4FFM3sxwNC8sT7I7IcIT4biXeBf5S/3cE5dbs Q493Wf4GXjoAGNWUuP+W2Fo65EOEx8zQYhO5I68BmGK/EEFhSmhh5A4EuWCuc1cbTlQsgILn9 LJMbB+zwhcdznk5WENbuybO1/ASBob8H4qoVLSGHfyqL2An5XVaoFqAjirr8VHT3KxnaFHAuX XXt2YALP2ObLR84fzQ/+i6a7DKOKGvpZm0jYH7qhNBUzXrgqbMtyCPZXAuuXzY2e3mM5BeZ/D fCQmk0fmJPorHKqjTJPscwXlLv6iNyx+Kfot5Ncg8IPhcWL7kJbRvG0H038cJymwpvQDC7KEs PjtH2Mrfkf9sP7pA5dHyNhrf1o3okXneKDMCJYNQr6gWm6IdZULSyQJWAsKVxKntlOFGoAuqd rdaxDWJq8MXVIJx8Ebo+A3JAVkMdy2mrA6mTgquJT+ZsOxe6JxoLTNw8pTMf8IChfCB/uZMsX M5SGqIyUdQGSasXFNYqm4yW0XxNuKKOlLExelmv0bo6mh5H+2PA/j1UbFawl1TZv08h8w/QBa wHoIT6U+XdN+iTbkd+c1nJng+aqghNKagWSFV56tzkWUrPuHh89LrbQs6ZiCmfmf4YZazqMiQ tOoRfAdiIecRqsUYxY9WRk7BFLg9AAM1k8437hP4jc3yz/3l1vcy+iOxH/lo2nZ+gpgozIuPw XRUNJerr2z5BpU5ULEW5gG6yaX4m7CaB6FzWJyYh2N2yjHmw1EIPSJ96U6CyxwXi8G3YHU4jW GtiCR2ETYJ9FdJ6Bh0q5DAtsar+MAOt1Yl5JyJ5CxNGgkxEwwMm1+oKOA== Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add basic support for RS485: Provide a callback to configure rs485 settings. Handle the RS485 specific part in the functions pl011_rs485_tx_start() and pl011_rs485_tx_stop() which extend the generic start/stop callbacks. Beside via IOCTL from userspace RS485 can be enabled by means of the device tree property "rs485-enabled-at-boot-time". Signed-off-by: Lino Sanfilippo --- This patch has been tested with a Raspberry Pi CM3. drivers/tty/serial/amba-pl011.c | 143 +++++++++++++++++++++++++++++++- 1 file changed, 140 insertions(+), 3 deletions(-) base-commit: cd1245d75ce93b8fd206f4b34eb58bcfe156d5e9 diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 78682c12156a..36e8b938cdba 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -265,6 +265,8 @@ struct uart_amba_port { unsigned int old_cr; /* state during shutdown */ unsigned int fixed_baud; /* vendor-set fixed baud rate */ char type[12]; + bool rs485_tx_started; + unsigned int rs485_tx_drain_interval; /* usecs */ #ifdef CONFIG_DMA_ENGINE /* DMA stuff */ bool using_tx_dma; @@ -275,6 +277,8 @@ struct uart_amba_port { #endif }; +static unsigned int pl011_tx_empty(struct uart_port *port); + static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, unsigned int reg) { @@ -1282,6 +1286,34 @@ static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) #define pl011_dma_flush_buffer NULL #endif +static int pl011_rs485_tx_stop(struct uart_amba_port *uap) +{ + struct uart_port *port = &uap->port; + u32 cr; + + /* Wait until hardware tx queue is empty */ + while (!pl011_tx_empty(port)) + udelay(uap->rs485_tx_drain_interval); + + if (port->rs485.delay_rts_after_send) + mdelay(port->rs485.delay_rts_after_send); + + cr = pl011_read(uap, REG_CR); + + if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) + cr &= ~UART011_CR_RTS; + else + cr |= UART011_CR_RTS; + /* Disable the transmitter and reenable the transceiver */ + cr &= ~UART011_CR_TXE; + cr |= UART011_CR_RXE; + pl011_write(cr, uap, REG_CR); + + uap->rs485_tx_started = false; + + return 0; +} + static void pl011_stop_tx(struct uart_port *port) { struct uart_amba_port *uap = @@ -1290,6 +1322,9 @@ static void pl011_stop_tx(struct uart_port *port) uap->im &= ~UART011_TXIM; pl011_write(uap->im, uap, REG_IMSC); pl011_dma_tx_stop(uap); + + if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) + pl011_rs485_tx_stop(uap); } static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); @@ -1380,6 +1415,31 @@ static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, return true; } +static void pl011_rs485_tx_start(struct uart_amba_port *uap) +{ + struct uart_port *port = &uap->port; + u32 cr; + + /* Enable transmitter */ + cr = pl011_read(uap, REG_CR); + cr |= UART011_CR_TXE; + /* Disable receiver if half-duplex */ + if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) + cr &= ~UART011_CR_RXE; + + if (port->rs485.flags & SER_RS485_RTS_ON_SEND) + cr &= ~UART011_CR_RTS; + else + cr |= UART011_CR_RTS; + + pl011_write(cr, uap, REG_CR); + + if (port->rs485.delay_rts_before_send) + mdelay(port->rs485.delay_rts_before_send); + + uap->rs485_tx_started = true; +} + /* Returns true if tx interrupts have to be (kept) enabled */ static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) { @@ -1397,6 +1457,10 @@ static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) return false; } + if ((uap->port.rs485.flags & SER_RS485_ENABLED) && + !uap->rs485_tx_started) + pl011_rs485_tx_start(uap); + /* If we are using DMA mode, try to send some characters. */ if (pl011_dma_tx_irq(uap)) return true; @@ -1542,6 +1606,9 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) container_of(port, struct uart_amba_port, port); unsigned int cr; + if (port->rs485.flags & SER_RS485_ENABLED) + mctrl &= ~TIOCM_RTS; + cr = pl011_read(uap, REG_CR); #define TIOCMBIT(tiocmbit, uartbit) \ @@ -1763,7 +1830,17 @@ static int pl011_startup(struct uart_port *port) /* restore RTS and DTR */ cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); - cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; + cr |= UART01x_CR_UARTEN | UART011_CR_RXE; + + if (port->rs485.flags & SER_RS485_ENABLED) { + if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) + cr &= ~UART011_CR_RTS; + else + cr |= UART011_CR_RTS; + } else { + cr |= UART011_CR_TXE; + } + pl011_write(cr, uap, REG_CR); spin_unlock_irq(&uap->port.lock); @@ -1864,6 +1941,9 @@ static void pl011_shutdown(struct uart_port *port) pl011_dma_shutdown(uap); + if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) + pl011_rs485_tx_stop(uap); + free_irq(uap->port.irq, uap); pl011_disable_uart(uap); @@ -1941,6 +2021,7 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, unsigned int lcr_h, old_cr; unsigned long flags; unsigned int baud, quot, clkdiv; + unsigned int bits; if (uap->vendor->oversampling) clkdiv = 8; @@ -1968,25 +2049,32 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, switch (termios->c_cflag & CSIZE) { case CS5: lcr_h = UART01x_LCRH_WLEN_5; + bits = 7; break; case CS6: lcr_h = UART01x_LCRH_WLEN_6; + bits = 8; break; case CS7: lcr_h = UART01x_LCRH_WLEN_7; + bits = 9; break; default: // CS8 lcr_h = UART01x_LCRH_WLEN_8; + bits = 10; break; } - if (termios->c_cflag & CSTOPB) + if (termios->c_cflag & CSTOPB) { lcr_h |= UART01x_LCRH_STP2; + bits++; + } if (termios->c_cflag & PARENB) { lcr_h |= UART01x_LCRH_PEN; if (!(termios->c_cflag & PARODD)) lcr_h |= UART01x_LCRH_EPS; if (termios->c_cflag & CMSPAR) lcr_h |= UART011_LCRH_SPS; + bits++; } if (uap->fifosize > 1) lcr_h |= UART01x_LCRH_FEN; @@ -1997,12 +2085,21 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, * Update the per-port timeout. */ uart_update_timeout(port, termios->c_cflag, baud); + /* + * Calculate the approximated time it takes to transmit one character + * with the given baud rate. We use this as the poll interval when we + * wait for the tx queue to empty. + */ + uap->rs485_tx_drain_interval = (bits * 1000 * 1000) / baud; pl011_setup_status_masks(port, termios); if (UART_ENABLE_MS(port, termios->c_cflag)) pl011_enable_ms(port); + if (port->rs485.flags & SER_RS485_ENABLED) + termios->c_cflag &= ~CRTSCTS; + /* first, disable everything */ old_cr = pl011_read(uap, REG_CR); pl011_write(0, uap, REG_CR); @@ -2124,6 +2221,41 @@ static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) return ret; } +static int pl011_rs485_config(struct uart_port *port, + struct serial_rs485 *rs485) +{ + struct uart_amba_port *uap = + container_of(port, struct uart_amba_port, port); + + /* pick sane settings if the user hasn't */ + if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) == + !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) { + rs485->flags |= SER_RS485_RTS_ON_SEND; + rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; + } + + rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 1000U); + rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 1000U); + memset(rs485->padding, 0, sizeof(rs485->padding)); + + if (port->rs485.flags & SER_RS485_ENABLED) + pl011_rs485_tx_stop(uap); + + /* Set new configuration */ + port->rs485 = *rs485; + /* Make sure auto RTS is disabled */ + if (port->rs485.flags & SER_RS485_ENABLED) { + u32 cr = pl011_read(uap, REG_CR); + + cr &= ~UART011_CR_RTSEN; + pl011_write(cr, uap, REG_CR); + port->status &= ~UPSTAT_AUTORTS; + } + + + return 0; +} + static const struct uart_ops amba_pl011_pops = { .tx_empty = pl011_tx_empty, .set_mctrl = pl011_set_mctrl, @@ -2592,6 +2724,7 @@ static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, struct resource *mmiobase, int index) { void __iomem *base; + int ret; base = devm_ioremap_resource(dev, mmiobase); if (IS_ERR(base)) @@ -2608,6 +2741,10 @@ static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, uap->port.flags = UPF_BOOT_AUTOCONF; uap->port.line = index; + ret = uart_get_rs485_mode(&uap->port); + if (ret) + return ret; + amba_ports[index] = uap; return 0; @@ -2665,7 +2802,7 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id) uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; uap->port.irq = dev->irq[0]; uap->port.ops = &amba_pl011_pops; - + uap->port.rs485_config = pl011_rs485_config; snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);