From patchwork Mon Sep 13 17:38:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 511414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4121C433F5 for ; Mon, 13 Sep 2021 17:38:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C0CC1610CC for ; Mon, 13 Sep 2021 17:38:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345122AbhIMRkC (ORCPT ); Mon, 13 Sep 2021 13:40:02 -0400 Received: from inva020.nxp.com ([92.121.34.13]:44000 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245147AbhIMRjw (ORCPT ); Mon, 13 Sep 2021 13:39:52 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id B7BE31A0393; Mon, 13 Sep 2021 19:38:34 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id AA73A1A038F; Mon, 13 Sep 2021 19:38:34 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id DA8BE20363; Mon, 13 Sep 2021 19:38:33 +0200 (CEST) From: Abel Vesa To: Rob Herring , Dong Aisheng , Shawn Guo , Sascha Hauer , Fabio Estevam , "catalin.marinas@arm.com" , Will Deacon , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Georgi Djakov , Adrian Hunter , Ulf Hansson , Ahmad Fatoum Cc: Pengutronix Kernel Team , linux-serial@vger.kernel.org, NXP Linux Team , Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Abel Vesa Subject: [RFC 14/19] arm64: dts: imx8mq: Add all pl301 nodes Date: Mon, 13 Sep 2021 20:38:09 +0300 Message-Id: <1631554694-9599-15-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631554694-9599-1-git-send-email-abel.vesa@nxp.com> References: <1631554694-9599-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add all the pl301s found on i.MX8MQ, according to the bus diagram. Each pl301 has its own clock, icc id and opp table. They are probed by the imx-bus driver. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 202 ++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index ab528665a217..a05bccbb1342 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1566,5 +1566,207 @@ ddr-pmu@3d800000 { interrupt-parent = <&gic>; interrupts = ; }; + + pl301_main: pl301@0 { + compatible = "fsl,imx8m-nic"; + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; + operating-points-v2 = <&pl301_main_opp_table>; + #interconnect-cells = <0>; + fsl,icc-id = ; + + pl301_main_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-133M { + opp-hz = /bits/ 64 <133333333>; + }; + opp-333M { + opp-hz = /bits/ 64 <333333333>; + }; + }; + }; + + pl301_enet: pl301@1 { + compatible = "fsl,imx8m-nic"; + clocks = <&clk IMX8MQ_CLK_ENET_AXI>; + operating-points-v2 = <&pl301_enet_opp_table>; + #interconnect-cells = <0>; + fsl,icc-id = ; + + pl301_enet_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-266M { + opp-hz = /bits/ 64 <266666666>; + }; + }; + }; + + pl301_gpu: pl301@2 { + compatible = "fsl,imx8m-nic"; + clocks = <&clk IMX8MQ_CLK_GPU_AXI>; + operating-points-v2 = <&pl301_gpu_opp_table>; + #interconnect-cells = <0>; + fsl,icc-id = ; + + pl301_gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; + }; + + pl301_dc: pl301@3 { + compatible = "fsl,imx8m-nic"; + clocks = <&clk IMX8MQ_CLK_DISP_AXI>; + operating-points-v2 = <&pl301_dc_opp_table>; + #interconnect-cells = <0>; + fsl,icc-id = ; + + pl301_dc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; + }; + + /* PL301_DISPLAY (IPs other than DCSS, inside SUPERMIX) */ + pl301_display: pl301@4 { + compatible = "fsl,imx8m-nic"; + /* FIXME: don't know which clock yet */ + clocks = <&clk IMX8MQ_CLK_DUMMY>; + operating-points-v2 = <&pl301_display_opp_table>; + #interconnect-cells = <0>; + fsl,icc-id = ; + + pl301_display_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-333M { + opp-hz = /bits/ 64 <333333333>; + }; + }; + }; + + pl301_audio: pl301@5 { + compatible = "fsl,imx8m-nic"; + clocks = <&clk IMX8MQ_CLK_AUDIO_AHB>; + operating-points-v2 = <&pl301_audio_opp_table>; + #interconnect-cells = <0>; + fsl,icc-id = ; + + pl301_audio_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-500M { + opp-hz = /bits/ 64 <500000000>; + }; + }; + }; + + pl301_video: pl301@6 { + compatible = "fsl,imx8m-nic"; + clocks = <&clk IMX8MQ_CLK_VPU_BUS>; + operating-points-v2 = <&pl301_video_opp_table>; + #interconnect-cells = <0>; + fsl,icc-id = ; + + pl301_video_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-500M { + opp-hz = /bits/ 64 <500000000>; + }; + }; + }; + + pl301_usb: pl301@7 { + compatible = "fsl,imx8m-nic"; + clocks = <&clk IMX8MQ_CLK_USB_BUS>; + operating-points-v2 = <&pl301_usb_opp_table>; + #interconnect-cells = <0>; + fsl,icc-id = ; + + pl301_usb_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-128M { + opp-hz = /bits/ 64 <128000000>; + }; + opp-500M { + opp-hz = /bits/ 64 <500000000>; + }; + }; + }; + + pl301_wakeup: pl301@8 { + compatible = "fsl,imx8m-nic"; + /* FIXME: don't know which clock yet */ + clocks = <&clk IMX8MQ_CLK_DUMMY>; + operating-points-v2 = <&pl301_wakeup_opp_table>; + #interconnect-cells = <0>; + fsl,icc-id = ; + + pl301_wakeup_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-133M { + opp-hz = /bits/ 64 <133333333>; + }; + }; + }; + + pl301_per_m: pl301@9 { + compatible = "fsl,imx8m-nic"; + clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS>; + operating-points-v2 = <&pl301_per_m_opp_table>; + #interconnect-cells = <0>; + fsl,icc-id = ; + + pl301_per_m_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-133M { + opp-hz = /bits/ 64 <133333333>; + }; + opp-266M { + opp-hz = /bits/ 64 <266666666>; + }; + }; + }; }; };