| Message ID | 20250120130936.1080069-1-claudiu.beznea.uj@bp.renesas.com |
|---|---|
| Headers | show |
| Series | Add support for the rest of Renesas RZ/G3S serial interfaces | expand |
On 20/01/2025 14:09, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > The Renesas RZ/G3S supports a power saving mode where power to most of the > SoC components is turned off. When returning from this power saving mode, > SoC components need to be re-configured. > > The SCIFs on the Renesas RZ/G3S need to be re-configured as well when > returning from this power saving mode. The sh-sci code already configures > the SCIF clocks, power domain and registers by calling uart_resume_port() > in sci_resume(). On suspend path the SCIF UART ports are suspended > accordingly (by calling uart_suspend_port() in sci_suspend()). The only > missing setting is the reset signal. For this assert/de-assert the reset > signal on driver suspend/resume. > > In case the no_console_suspend is specified by the user, the registers need > to be saved on suspend path and restore on resume path. To do this the > sci_console_setup() function was added. There is no need to cache/restore > the status or FIFO registers. Only the control registers. To differentiate > b/w these, the struct sci_port_params::regs was updated with a new member > that specifies if the register needs to be chached on suspend. Only the > RZ_SCIFA instances were updated with this new support as the hardware for > the rest of variants was missing for testing. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v4: > - none Why are you combining serial patches with DTS? Greg applies entire set thus you *cannot* send him DTS. Best regards, Krzysztof
On 21.01.2025 10:54, Krzysztof Kozlowski wrote: > On 20/01/2025 14:09, Claudiu wrote: >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> The Renesas RZ/G3S supports a power saving mode where power to most of the >> SoC components is turned off. When returning from this power saving mode, >> SoC components need to be re-configured. >> >> The SCIFs on the Renesas RZ/G3S need to be re-configured as well when >> returning from this power saving mode. The sh-sci code already configures >> the SCIF clocks, power domain and registers by calling uart_resume_port() >> in sci_resume(). On suspend path the SCIF UART ports are suspended >> accordingly (by calling uart_suspend_port() in sci_suspend()). The only >> missing setting is the reset signal. For this assert/de-assert the reset >> signal on driver suspend/resume. >> >> In case the no_console_suspend is specified by the user, the registers need >> to be saved on suspend path and restore on resume path. To do this the >> sci_console_setup() function was added. There is no need to cache/restore >> the status or FIFO registers. Only the control registers. To differentiate >> b/w these, the struct sci_port_params::regs was updated with a new member >> that specifies if the register needs to be chached on suspend. Only the >> RZ_SCIFA instances were updated with this new support as the hardware for >> the rest of variants was missing for testing. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> --- >> >> Changes in v4: >> - none > > > Why are you combining serial patches with DTS? Greg applies entire set > thus you *cannot* send him DTS. It's v4. The initial set contained fixes for serial, support for RZ/G3S (including clocks and dtsi), all that was needed for the enabled RZ/G3S serial IPs. Fixes were posted separately (as requested), the other bringup patches were integrated and this is what remained. I chose it like this for version continuity. Thank you, Claudiu > > Best regards, > Krzysztof
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Hi, The Renesas RZ/G3S SoC has 6 serial interfaces. One of them is used as debug console (and it is already enabled in the current code base). Series adds support for the remaining ones. Patches: - 01/04 - extends suspend to RAM support on the serial driver for the RZ/G3S SoC - 02-04/04 - add device tree support Merge strategy, if any: - patch 01/04 can go through the serial tree - patches 02-04/04 can go through the Renesas tree Thank you, Claudiu Beznea Changes in v4: - dropped fixes and clock patches as they were applied independently - dropped DT patches that were already applied - addressed review comments Changes in v3: - in patch "serial: sh-sci: Check if TX data was written to device in .tx_empty()": -- check the status of the DMA transaction in tx_empty() -- changed the variable name that tracks if TX occurred Changes in v2: - drop patch "serial: sh-sci: Clean sci_ports[0] after at earlycon exit" from v1 as it was already applied - used bool instead of atomic_t in patch "serial: sh-sci: Check if TX data was written to device in .tx_empty()" Claudiu Beznea (4): serial: sh-sci: Update the suspend/resume support arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches arm64: dts: renesas: rzg3s-smarc: Enable SCIF3 arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1 arch/arm64/boot/dts/renesas/Makefile | 3 ++ .../r9a08g045s33-smarc-pmod1-type-3a.dtso | 48 +++++++++++++++++ .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 20 +------ .../boot/dts/renesas/rzg3s-smarc-switches.h | 40 ++++++++++++++ arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 13 +++++ drivers/tty/serial/sh-sci.c | 53 +++++++++++++++---- 6 files changed, 149 insertions(+), 28 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h