[0/2] add NXP LINFlexD UART clock support for S32G2/S32G3 SoC

Message ID	20240924141247.132455-1-ciprianmarian.costea@oss.nxp.com
Headers	show Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2068.outbound.protection.outlook.com [40.107.22.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1549E1B85D5; Tue, 24 Sep 2024 14:12:58 +0000 (UTC) From: Ciprian Costea <ciprianmarian.costea@oss.nxp.com> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Chester Lin <chester62515@gmail.com> Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, NXP S32 Linux Team <s32@nxp.com>, Christophe Lizzi <clizzi@redhat.com>, Alberto Ruiz <aruizrui@redhat.com>, Enric Balletbo <eballetb@redhat.com>, Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Subject: [PATCH 0/2] add NXP LINFlexD UART clock support for S32G2/S32G3 SoC Date: Tue, 24 Sep 2024 17:12:45 +0300 Message-ID: <20240924141247.132455-1-ciprianmarian.costea@oss.nxp.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1
Series	add NXP LINFlexD UART clock support for S32G2/S32G3 SoC \| expand [0/2] add NXP LINFlexD UART clock support for S32G2/S32G3 SoC [1/2] dt-bindings: linflexuart: add clock definitions [2/2] serial: fsl_linflexuart: add clock support

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20240924141247.132455-1-ciprianmarian.costea@oss.nxp.com

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From: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jiri Slaby <jirislaby@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Chester Lin <chester62515@gmail.com>
Cc: linux-kernel@vger.kernel.org,
	linux-serial@vger.kernel.org,
	devicetree@vger.kernel.org,
	NXP S32 Linux Team <s32@nxp.com>,
	Christophe Lizzi <clizzi@redhat.com>,
	Alberto Ruiz <aruizrui@redhat.com>,
	Enric Balletbo <eballetb@redhat.com>,
	Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Subject: [PATCH 0/2] add NXP LINFlexD UART clock support for S32G2/S32G3 SoC
Date: Tue, 24 Sep 2024 17:12:45 +0300
Message-ID: <20240924141247.132455-1-ciprianmarian.costea@oss.nxp.com>
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Series

add NXP LINFlexD UART clock support for S32G2/S32G3 SoC | expand

Message

Ciprian Costea Sept. 24, 2024, 2:12 p.m. UTC

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

LINFlexD UART driver is used by S32 SoC family.
Add clocking support as optional in order to not break
existing support for S32V234 SoC.

A separate patch adding clock definitions to
the S32G2/S32G3 based boards devicetree will be sent
for review.

Ciprian Marian Costea (2):
  dt-bindings: linflexuart: add clock definitions
  serial: fsl_linflexuart: add clock support

 .../bindings/serial/fsl,s32-linflexuart.yaml  | 21 ++++++
 drivers/tty/serial/fsl_linflexuart.c          | 67 ++++++++++++++-----
 2 files changed, 72 insertions(+), 16 deletions(-)