| Message ID | 20250113-sm8750_ufs_master-v1-4-b3774120eb8c@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/5] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY | expand |
On Mon, Jan 13, 2025 at 01:46:27PM -0800, Melody Olvera wrote: > From: Nitin Rawat <quic_nitirawa@quicinc.com> > > Add UFS host controller and PHY nodes for SM8750 SoC. > > Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> > Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 81 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 81 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi > index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..20690c102244b337847a6482dd83c37e19746de9 100644 > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > @@ -13,6 +13,7 @@ > #include <dt-bindings/power/qcom,rpmhpd.h> > #include <dt-bindings/power/qcom-rpmpd.h> > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > +#include <dt-bindings/gpio/gpio.h> > > / { > interrupt-parent = <&intc>; > @@ -1939,6 +1940,86 @@ mmss_noc: interconnect@1780000 { > #interconnect-cells = <2>; > }; > > + ufs_mem_phy: phy@1d80000 { > + compatible = "qcom,sm8750-qmp-ufs-phy"; > + reg = <0x0 0x01d80000 0x0 0x2000>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > + <&tcsrcc TCSR_UFS_CLKREF_EN>; > + clock-names = "ref", > + "ref_aux", > + "qref"; > + > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + > + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + ufs_mem_hc: ufs@1d84000 { > + compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; > + reg = <0x0 0x01d84000 0x0 0x3000>; > + > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&rpmhcc RPMH_LN_BB_CLK3>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; > + freq-table-hz = <100000000 403000000>, > + <0 0>, > + <0 0>, > + <100000000 403000000>, > + <100000000 403000000>, > + <0 0>, > + <0 0>, > + <0 0>; Use OPP table instead > + > + resets = <&gcc GCC_UFS_PHY_BCR>; > + reset-names = "rst"; > + > + > + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; Shouldn't cpu-ufs be ACTIVE_ONLY? > + interconnect-names = "ufs-ddr", > + "cpu-ufs"; > + > + power-domains = <&gcc GCC_UFS_PHY_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + > + iommus = <&apps_smmu 0x60 0>; > + dma-coherent; > + > + lanes-per-direction = <2>; > + > + phys = <&ufs_mem_phy>; > + phy-names = "ufsphy"; > + > + #reset-cells = <1>; > + > + status = "disabled"; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x20000>; > > -- > 2.46.1 >
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..20690c102244b337847a6482dd83c37e19746de9 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/gpio/gpio.h> / { interrupt-parent = <&intc>; @@ -1939,6 +1940,86 @@ mmss_noc: interconnect@1780000 { #interconnect-cells = <2>; }; + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,sm8750-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <100000000 403000000>, + <0 0>, + <0 0>, + <100000000 403000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x60 0>; + dma-coherent; + + lanes-per-direction = <2>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>;