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Bottomley" , "Martin K. Petersen" , Nitin Rawat , Can Guo , Naveen Kumar Goud Arepalli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1292; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=sny/m9wJ9i9gQI3uK7sG9rC2WxbHvJ9BZkJpg0lVtPU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlxp4oF/udIPmh25v9YaVBGF8zomk/oAgu82oWc 4qjt3F9Vo+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZcaeKAAKCRCLPIo+Aiko 1fqJB/9MX9MZSLldZwM1esOwZZgWaY816oeEp0Kz6LtZi4kAPH483880Np+n7VHQz00nlQTGwMa IGHIxyL0OV132G+to0mZ68vDXrPlIiecUxo5fUADw5Dl6QIyp0cLW8ewj91Rzp3b4fI3TM8HOBC Y87B+sdiwznm3ZENyUcd89xkUaILfIO5xpMsd0aweNTjiwTbpNgG0AufCvU8WldZgMF+rwwd5A0 VlzGssDcpOiEWB4+4Jg6GfS95/0XgKn5tmhDyX+LFrPOKR17CTJ7f6r1DQOFQgmuO0BaP3e9uqE mCjM+v3umfKHqUMCWfOFKaVLnzbDXn00pzmPmeXTh823Fean X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The MSM8996 DT doesn't provide frequency limits for the core_clk_unipro clock, which results in miscalculation of the cycles_in_1us value. Provide the backwards-compatible default to support existing MSM8996 DT files. Fixes: b4e13e1ae95e ("scsi: ufs: qcom: Add multiple frequency support for MAX_CORE_CLK_1US_CYCLES") Cc: Nitin Rawat Signed-off-by: Dmitry Baryshkov --- drivers/ufs/host/ufs-qcom.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 0aeaee1c564c..79f8cb377710 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1210,8 +1210,10 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) list_for_each_entry(clki, head, list) { if (!IS_ERR_OR_NULL(clki->clk) && - !strcmp(clki->name, "core_clk_unipro")) { - if (is_scale_up) + !strcmp(clki->name, "core_clk_unipro")) { + if (!clki->max_freq) + cycles_in_1us = 150; /* default for backwards compatibility */ + else if (is_scale_up) cycles_in_1us = ceil(clki->max_freq, (1000 * 1000)); else cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000));