From patchwork Wed Jul 12 10:32:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 704883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CF49EB64D9 for ; Wed, 12 Jul 2023 10:54:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232126AbjGLKyh (ORCPT ); Wed, 12 Jul 2023 06:54:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229640AbjGLKyg (ORCPT ); Wed, 12 Jul 2023 06:54:36 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA514E5C for ; Wed, 12 Jul 2023 03:54:35 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1b9de2bd0abso16997185ad.0 for ; Wed, 12 Jul 2023 03:54:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689159275; x=1691751275; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:resent-to:resent-message-id :resent-date:resent-from:from:to:cc:subject:date:message-id:reply-to; bh=WUaVdZJ28qH1inEDT0bdOsxGBg7b/AdUYV5SKgyveWU=; b=nVVkayUUO474FBrI4EiA6njLK8DKaPJMYY9bDRhLoGjGPymZqzYwwC+Q/eTeE6XyVc +RbpNP3ERLZhqSzWn9lamVkxHa7RGnvs4PNDqwYteW3P1WfmNYB+IlQrnL21MV4oyuXO dTPEdWq8afT/U/LVwcGU9fuOTbdLLVpaAKWkoO+qFtgyAx1z9RmFO5JkB5nzHiAbV2BW lWmQ4WbUaUSiTHO9omjpPONpLt0kheQDIQ3W5wWejPiNqY0SzyBJEG8L+5dtzEFLvzAl D3jA8Zg8HhXktt5BQ+JrifLzMrIPTyfMALb0zlWrnU46WTXAdjDK3fGaqXDnOsJH95HT E5Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689159275; x=1691751275; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:resent-to:resent-message-id :resent-date:resent-from:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=WUaVdZJ28qH1inEDT0bdOsxGBg7b/AdUYV5SKgyveWU=; b=e9ZKY59TKXTOhH6ZjOg5PwD0ojIgFLSNs4iTk3h9nq8XL5hl+bBRQV2zNQwface0YT ukT8VKbQeVx6k5f6m0sDPvj6XZlHalIwaicWY4MuVpjb1/Ds/WTaZtWXWE3thC3wn24J +u0j2JCnEJ1Mj7MKfd9PiAYXqkA5Rztwl5bD9ke4Gqwvk/hAf5lFlhYYmlhafQjYbn7w l303s0hJuTRP9jcxiC8LCuQYYlYmYWSvDiiyIWdZ8MQSbzoE9DKctZvH+qrwy88Xf16B Afskn7JhY9obItlwkiDjIrsk4CgxF+UIkuq55YGBvGpezK3XdUtPB4qY9KlG4Gjm3KCW nT1A== X-Gm-Message-State: ABy/qLZ2bAkunxiYBmxozFI57mtiHNiNPQOnrbgZqfZerzNy/4Ef+U9H qnXKXFeFZXcyj4GL+fmn4ZdH X-Google-Smtp-Source: APBJJlHsjKcgTbUic2wsleVFH+Pv10DBW2I0NrRhAaOGgZqL8Ea7bwGt08by59DvZHPfWznGk92tRA== X-Received: by 2002:a17:902:d509:b0:1b7:facb:2e79 with SMTP id b9-20020a170902d50900b001b7facb2e79mr17257247plg.18.1689159275291; Wed, 12 Jul 2023 03:54:35 -0700 (PDT) Received: from thinkpad ([117.207.27.131]) by smtp.gmail.com with ESMTPSA id u4-20020a170902e5c400b001b54dcd84e2sm2210726plf.240.2023.07.12.03.54.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 03:54:35 -0700 (PDT) Received: from localhost.localdomain ([117.207.27.131]) by smtp.gmail.com with ESMTPSA id k15-20020aa790cf000000b00666b3706be6sm3247860pfk.107.2023.07.12.03.33.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 03:33:38 -0700 (PDT) From: Manivannan Sadhasivam To: vireshk@kernel.org, nm@ti.com, sboyd@kernel.org, myungjoo.ham@samsung.com, kyungmin.park@samsung.com, cw00.choi@samsung.com, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, quic_asutoshd@quicinc.com, quic_cang@quicinc.com, quic_nitirawa@quicinc.com, quic_narepall@quicinc.com, quic_bhaskarv@quicinc.com, quic_richardp@quicinc.com, quic_nguyenb@quicinc.com, quic_ziqichen@quicinc.com, bmasney@redhat.com, krzysztof.kozlowski@linaro.org, Manivannan Sadhasivam Subject: [PATCH 05/14] arm64: dts: qcom: sdm845: Add OPP table support to UFSHC Date: Wed, 12 Jul 2023 16:02:00 +0530 Message-Id: <20230712103213.101770-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230712103213.101770-1-manivannan.sadhasivam@linaro.org> References: <20230712103213.101770-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-TUID: qyaSTK9jD1y7 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Krzysztof Kozlowski UFS host controller, when scaling gears, should choose appropriate performance state of RPMh power domain controller along with clock frequency. So let's add the OPP table support to specify both clock frequency and RPMh performance states replacing the old "freq-table-hz" property. Signed-off-by: Krzysztof Kozlowski [mani: Splitted pd change and used rpmhpd_opp_low_svs] Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 41 +++++++++++++++++++++------- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 89520a9fe1e3..e04a3cbb1017 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2605,18 +2605,39 @@ ufs_mem_hc: ufshc@1d84000 { <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <75000000 300000000>; + operating-points-v2 = <&ufs_opp_table>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <37500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ufs_mem_phy: phy@1d87000 {