From patchwork Wed Oct 26 07:39:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?RWRkaWUgSHVhbmcgKOm7g+aZuuWCkSk=?= X-Patchwork-Id: 619141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8088FFA3742 for ; Wed, 26 Oct 2022 07:40:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233268AbiJZHkI (ORCPT ); Wed, 26 Oct 2022 03:40:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233242AbiJZHkF (ORCPT ); Wed, 26 Oct 2022 03:40:05 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BDB713E16 for ; Wed, 26 Oct 2022 00:39:58 -0700 (PDT) X-UUID: 2a2dcd859ad243e99f3b3b6c58f89286-20221026 DKIM-Signature: v=1; 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Wed, 26 Oct 2022 15:39:51 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 26 Oct 2022 15:39:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 26 Oct 2022 15:39:50 +0800 From: Eddie Huang To: Asutosh Das , , , , CC: , , , , , Eddie Huang Subject: [PATCH v1 2/2] ufs: mtk-host: Add MCQ feature Date: Wed, 26 Oct 2022 15:39:43 +0800 Message-ID: <20221026073943.22111-3-eddie.huang@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20221026073943.22111-1-eddie.huang@mediatek.com> References: <20221026073943.22111-1-eddie.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Add Mediatek mcq resource and runtime configuration function to support MCQ capability Signed-off-by: Eddie Huang --- drivers/ufs/host/ufs-mediatek.c | 37 +++++++++++++++++++++++++++++++++++++ drivers/ufs/host/ufs-mediatek.h | 7 +++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index c958279..3f5fc05 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -31,6 +31,8 @@ #define CREATE_TRACE_POINTS #include "ufs-mediatek-trace.h" +#define MCQ_QUEUE_OFFSET(c) ((((c) >> 16) & 0xFF) * 0x200) + static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = { { .wmanufacturerid = UFS_ANY_VENDOR, .model = UFS_ANY_MODEL, @@ -833,6 +835,8 @@ static int ufs_mtk_init(struct ufs_hba *hba) host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER); + hba->caps |= UFSHCD_CAP_MCQ_EN; + goto out; out_variant_clear: @@ -1314,6 +1318,37 @@ static void ufs_mtk_event_notify(struct ufs_hba *hba, trace_ufs_mtk_event(evt, val); } +static int ufs_mtk_op_runtime_config(struct ufs_hba *hba) +{ + struct ufshcd_mcq_opr_info_t *opr; + int i; + + for (i = 0; i < OPR_MAX; i++) { + opr = &hba->mcq_opr[i]; + opr->stride = REG_UFS_MCQ_STRIDE; + } + + hba->mcq_opr[OPR_SQD].offset = REG_UFS_MTK_SQD; + hba->mcq_opr[OPR_SQIS].offset = REG_UFS_MTK_SQIS; + hba->mcq_opr[OPR_CQD].offset = REG_UFS_MTK_CQD; + hba->mcq_opr[OPR_CQIS].offset = REG_UFS_MTK_CQIS; + + hba->mcq_opr[OPR_SQD].base = hba->mmio_base + REG_UFS_MTK_SQD; + hba->mcq_opr[OPR_SQIS].base = hba->mmio_base + REG_UFS_MTK_SQIS; + hba->mcq_opr[OPR_CQD].base = hba->mmio_base + REG_UFS_MTK_CQD; + hba->mcq_opr[OPR_CQIS].base = hba->mmio_base + REG_UFS_MTK_CQIS; + + return 0; +} + +static int ufs_mtk_config_mcq_resource(struct ufs_hba *hba) +{ + hba->mcq_base = hba->mmio_base + + MCQ_QUEUE_OFFSET(hba->mcq_capabilities); + + return 0; +} + /* * struct ufs_hba_mtk_vops - UFS MTK specific variant operations * @@ -1335,6 +1370,8 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = { .dbg_register_dump = ufs_mtk_dbg_register_dump, .device_reset = ufs_mtk_device_reset, .event_notify = ufs_mtk_event_notify, + .op_runtime_config = ufs_mtk_op_runtime_config, + .config_mcq_resource = ufs_mtk_config_mcq_resource, }; /** diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h index aa26d41..febf702 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -26,6 +26,13 @@ #define REG_UFS_DEBUG_SEL_B2 0x22D8 #define REG_UFS_DEBUG_SEL_B3 0x22DC +#define REG_UFS_MTK_SQD 0x2800 +#define REG_UFS_MTK_SQIS 0x2814 +#define REG_UFS_MTK_CQD 0x281C +#define REG_UFS_MTK_CQIS 0x2824 + +#define REG_UFS_MCQ_STRIDE 0x30 + /* * Ref-clk control *