From patchwork Mon Sep 12 13:57:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sreekanth Reddy X-Patchwork-Id: 605242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EE9BECAAD5 for ; Mon, 12 Sep 2022 13:45:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229923AbiILNpo (ORCPT ); Mon, 12 Sep 2022 09:45:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229561AbiILNpg (ORCPT ); Mon, 12 Sep 2022 09:45:36 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23C411CFCD for ; Mon, 12 Sep 2022 06:45:33 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id m3so8126507pjo.1 for ; Mon, 12 Sep 2022 06:45:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date; bh=Pq6t3y1inB024n03NV+rzOjSt8qvQc/pVIQNNBZYI/A=; b=PUrIKKfcmPBLkGXvReCRwGfrSjSbIb9tx05b0Y4ZETgASKBp7t4GlnYLWcfLkmjquW ywsBl7dkjemEug3jhMyyiQLLqQDXq6p/8MC5fBOHZSJIsr0Jw4xTjSAKiQbGQdP2Xoxq wAS73Dj1iV7Ug2dK1l9/8ZEQ/aOxHAp+Lmf+Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date; bh=Pq6t3y1inB024n03NV+rzOjSt8qvQc/pVIQNNBZYI/A=; b=xi24NF86ZwRaPn0I4jWmSVBc+c32xYs7uV7MvYqlpIY2ttqE6Sk03un2Brhir+mFUL nCry6GFZhXEwg6MkHpG2h+ybO/wfDVvzhQ/DVA2z4wzmJfztEDfmdLlwJtwtof++bjwh qQM2SxanumGx8dja2Z2a/ssBxCrsPh6ANfsN6Nv0ouyYZGR5CCgJ4Iv2tmDRrxuer3aO b5gr6z3FkjBmMfobACj/6DPLNHdraTYiedsXsAUrnnYG4ZVF9F2Of3jhXhHfSbQZ2cig t1oqocGdfINdMhgiQfByFhz+GzAeFQvmdrpxpYOlp9cM3wVNXpf6gsub3hFVWLk3oeP/ 2kOQ== X-Gm-Message-State: ACgBeo0v+j+MNyg5zA9IAODsPNcGLjxRqSn8lB045uo2CgC7Fi8rkEhI rkRsE9iKYX1qC5UhwmlY56V1oW8N0Ep6yCXitAI+Jn3VBczCV+u9/akzs/wTbFjTtnwTppfwln1 T5VnJHQd/+5XJCtjX/8TA28Q7C9k7sSzMwCdJdbP1MB9Tw4inJGZyerj4IK3Ccq3vYLJJwMPdwd q8sphMTwoA X-Google-Smtp-Source: AA6agR6gWEhmbYEk4H+AobVCV2bcRtZPKCWNIAumeDDELRI3V/uIbGnNkTKmUIg+bQhqxSknFH/Egw== X-Received: by 2002:a17:90b:3a82:b0:1fe:45db:2c2b with SMTP id om2-20020a17090b3a8200b001fe45db2c2bmr23564720pjb.102.1662990332104; Mon, 12 Sep 2022 06:45:32 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id u7-20020a170903124700b00176e8f85146sm6112900plh.185.2022.09.12.06.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 06:45:31 -0700 (PDT) From: Sreekanth Reddy To: linux-scsi@vger.kernel.org Cc: martin.petersen@oracle.com, Sreekanth Reddy Subject: [PATCH v2 3/9] mpi3mr: Schedule IRQ kthreads only on non-RT kernels Date: Mon, 12 Sep 2022 19:27:36 +0530 Message-Id: <20220912135742.11764-4-sreekanth.reddy@broadcom.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220912135742.11764-1-sreekanth.reddy@broadcom.com> References: <20220912135742.11764-1-sreekanth.reddy@broadcom.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org In RT kernels, the IRQ handler's code is executed as a kernel thread. So, the driver is modified not to explicitly schedule the IRQ kernel thread. Signed-off-by: Sreekanth Reddy --- drivers/scsi/mpi3mr/mpi3mr_fw.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/mpi3mr/mpi3mr_fw.c b/drivers/scsi/mpi3mr/mpi3mr_fw.c index cc700e2..78792f2 100644 --- a/drivers/scsi/mpi3mr/mpi3mr_fw.c +++ b/drivers/scsi/mpi3mr/mpi3mr_fw.c @@ -537,6 +537,7 @@ int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, if ((le16_to_cpu(reply_desc->reply_flags) & MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) break; +#ifndef CONFIG_PREEMPT_RT /* * Exit completion loop to avoid CPU lockup * Ensure remaining completion happens from threaded ISR. @@ -545,7 +546,7 @@ int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, op_reply_q->enable_irq_poll = true; break; } - +#endif } while (1); writel(reply_ci, @@ -614,6 +615,8 @@ static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata) return IRQ_NONE; } +#ifndef CONFIG_PREEMPT_RT + static irqreturn_t mpi3mr_isr(int irq, void *privdata) { struct mpi3mr_intr_info *intr_info = privdata; @@ -691,6 +694,8 @@ static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata) return IRQ_HANDLED; } +#endif + /** * mpi3mr_request_irq - Request IRQ and register ISR * @mrioc: Adapter instance reference @@ -713,8 +718,13 @@ static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index) snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d", mrioc->driver_name, mrioc->id, index); +#ifndef CONFIG_PREEMPT_RT retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr, mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info); +#else + retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary, + NULL, IRQF_SHARED, intr_info->name, intr_info); +#endif if (retval) { ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n", intr_info->name, pci_irq_vector(pdev, index)); @@ -2179,9 +2189,13 @@ int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, pi = 0; op_req_q->pi = pi; +#ifndef CONFIG_PREEMPT_RT if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios) > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT) mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true; +#else + atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios); +#endif writel(op_req_q->pi, &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);