From patchwork Wed Jun 22 07:37:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 584547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C80BC433EF for ; Wed, 22 Jun 2022 07:37:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353242AbiFVHhi (ORCPT ); Wed, 22 Jun 2022 03:37:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353217AbiFVHhc (ORCPT ); Wed, 22 Jun 2022 03:37:32 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF0CC377D6; Wed, 22 Jun 2022 00:37:27 -0700 (PDT) X-UUID: 9407edab5f7f45a78c1a8106f7f15b26-20220622 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6, REQID:763b9070-c475-4aae-bd6c-266f762701cf, OB:0, LO B:0,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:0 X-CID-META: VersionHash:b14ad71, CLOUDID:c8272738-5e4b-44d7-80b2-bb618cb09d29, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 9407edab5f7f45a78c1a8106f7f15b26-20220622 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 859568840; Wed, 22 Jun 2022 15:37:22 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 22 Jun 2022 15:37:21 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Jun 2022 15:37:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 22 Jun 2022 15:37:21 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v1 3/7] scsi: ufs-mediatek: Prevent host hang by setting CLK_CG early Date: Wed, 22 Jun 2022 15:37:15 +0800 Message-ID: <20220622073719.21599-4-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220622073719.21599-1-stanley.chu@mediatek.com> References: <20220622073719.21599-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Peter Wang Some UFSHCI hosts in MediaTek UFS platform need workaround to prevent host hang issue by setting CLK_CG bit before host is enabled. This operation shall have no side effect on those platforms which do not support this bit. Reviewed-by: Stanley Chu Signed-off-by: Peter Wang Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 8 ++++++++ drivers/ufs/host/ufs-mediatek.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index f76e2999ac99..d6b2734e7f81 100755 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -183,6 +183,14 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT; hba->ahit = 0; } + + /* + * Turn on CLK_CG early to bypass abnormal ERR_CHK signal + * to prevent host hang issue + */ + ufshcd_writel(hba, + ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80, + REG_UFS_XOUFS_CTRL); } return 0; diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h index 49a2137fb251..f5c1c643dd52 100755 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -12,6 +12,7 @@ /* * Vendor specific UFSHCI Registers */ +#define REG_UFS_XOUFS_CTRL 0x140 #define REG_UFS_REFCLK_CTRL 0x144 #define REG_UFS_EXTREG 0x2100 #define REG_UFS_MPHYCTRL 0x2200