From patchwork Fri Sep 11 03:37:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 296776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E87D8C433E2 for ; Fri, 11 Sep 2020 03:38:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B587321D81 for ; Fri, 11 Sep 2020 03:38:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Cv+Gcg9q" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725800AbgIKDiN (ORCPT ); Thu, 10 Sep 2020 23:38:13 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:59431 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725774AbgIKDht (ORCPT ); Thu, 10 Sep 2020 23:37:49 -0400 X-UUID: 37f86f7ef02e4ca1a2d72297214d09f2-20200911 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=/mYD66patFgq7ha/cJhn7mSkoKmWOdFvvY0fkbfVMfM=; b=Cv+Gcg9qMb1hXk4Px7oFdExxlSU0WCl0Oe9MVzsESHOs9A4Hdf4xS7BF/7jOA0473zywGO8F50aSloN7XRJ/9U9W/XFpgIcTxcNoWN9j/P2prhXNDd4DgTYpDrHrQaclbE2+xhW1hbN9gaG6H9483hdLXDbS9b/UJ8iYlwFzoiQ=; X-UUID: 37f86f7ef02e4ca1a2d72297214d09f2-20200911 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1128609697; Fri, 11 Sep 2020 11:37:46 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Sep 2020 11:37:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 11 Sep 2020 11:37:37 +0800 From: Stanley Chu To: , , , , , , , CC: , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v2 2/2] dt-bindings: ufs-mediatek: Add mt8192-ufshci compatible string Date: Fri, 11 Sep 2020 11:37:35 +0800 Message-ID: <20200911033735.21751-3-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200911033735.21751-1-stanley.chu@mediatek.com> References: <20200911033735.21751-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 0BB81318896B0759360427A59F7D86010AAC42047CB7D2214515CB89FB74033A2000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Add "mediatek,mt8192-ufshci" compatible string to for MediaTek UFS host controller present on MT8192 chipsets. Signed-off-by: Stanley Chu --- Documentation/devicetree/bindings/ufs/ufs-mediatek.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt b/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt index 72aab8547308..63a953b672d2 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt @@ -9,7 +9,9 @@ contain a phandle reference to UFS M-PHY node. Required properties for UFS nodes: - compatible : Compatible list, contains the following controller: "mediatek,mt8183-ufshci" for MediaTek UFS host controller - present on MT81xx chipsets. + present on MT8183 chipsets. + "mediatek,mt8192-ufshci" for MediaTek UFS host controller + present on MT8192 chipsets. - reg : Address and length of the UFS register set. - phys : phandle to m-phy. - clocks : List of phandle and clock specifier pairs.