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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id m85sm130301000pfj.171.2019.01.11.14.54.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Jan 2019 14:54:52 -0800 (PST) From: Bjorn Andersson To: Vinayak Holikatti , "James E.J. Bottomley" , "Martin K. Petersen" Cc: linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson Subject: [PATCH] scsi: ufs: Consider device limitations for dma_mask Date: Fri, 11 Jan 2019 14:54:02 -0800 Message-Id: <20190111225402.6133-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org On Qualcomm SDM845 the capabilities of the UFS MEM controller states that it's capable of dealing with 64 bit addresses, but DMA addresses are truncated causing IOMMU faults when trying to issue operations. Limit the DMA mask to that of the device, so that DMA allocations is limited to the range supported by the bus and device and not just following what the controller's capabilities states. Signed-off-by: Bjorn Andersson --- drivers/scsi/ufs/ufshcd.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) -- 2.18.0 diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 9ba7671b84f8..dc0eb59dd46f 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -8151,11 +8151,14 @@ EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); */ static int ufshcd_set_dma_mask(struct ufs_hba *hba) { - if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { - if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) - return 0; - } - return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); + u64 dma_mask = dma_get_mask(hba->dev); + + if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) + dma_mask &= DMA_BIT_MASK(64); + else + dma_mask &= DMA_BIT_MASK(32); + + return dma_set_mask_and_coherent(hba->dev, dma_mask); } /**