From patchwork Fri Dec 8 17:16:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 121198 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp863246qgn; Fri, 8 Dec 2017 08:31:18 -0800 (PST) X-Google-Smtp-Source: AGs4zMabHZwWLnB/d5pEs9E4PQ+7wgrQBJTKgULnYUt+lLVBlTy0vSLapUL4MQpESFHqHyjCJh5T X-Received: by 10.99.171.13 with SMTP id p13mr26146388pgf.30.1512750678908; Fri, 08 Dec 2017 08:31:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512750678; cv=none; d=google.com; s=arc-20160816; b=b41cL6Q6/kigY7fRTs0GrkikL1/A904uZyBqpZJ++zPq+gXstiJc7GsU3sTbya9MEd WBEfx1PvA4hJDrqwowlRIbrvUBER3xPKWDRuawUMHbbxUPdM2yyQcX2GnxSJSNDOkn/c 1wCQ8inNVzTTwunFYGlYdGi4HimkeQR0MnPXsLRimE9xMGKfGIQN1nYpqDTM8Gcuu2Zq A/qJ8GpkE3BBdTWPdPrr+hejRAhYDtgGujWYxfRDCQs1iu7vIlgMya7A2oi2F3+X9vPs 3REA9eF+ryQhKAIDUN3rSS6c1Aq8ykjIguSYUQL51M7L2ArIVQXtkKU0YF9rWUji+mE5 qWKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=/xwQ3sdK2/+tg5l8DVNQtDSO/TD6aeXyPb6VidFadHo=; b=Br+OyQUMY05qijJeAJqnm7lJWWn3og/8wSgppn1WGcQWE6ym4jw55lFK4NJ8uwX9DD KVr0qaFduuyuobiAWJRHOMUM3kHSoExBIRpkYtiFCoyKbxxyBnn9qEEqxUy7mFuBQg+S rwxhNZivCm6o/eK/oLbKZNSuXdRE/6p/CYkhRpyEPz/Qf4oiTgytRcwOKJh9layo0bdd XWFcdaBsWz2Ktq56no2V+DSi2olaYs6+AaCXuLsqAh6l3MoY8sAE5t+J7e5dx35rDuMJ oqN9b48Ftq4N+8zxes/k3VYmbCp6VxUkpAWRDFXHZYAmH9fNoKcYWuAKpn55+kuQB4K1 K3+w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o6si2289947pls.300.2017.12.08.08.31.18; Fri, 08 Dec 2017 08:31:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754627AbdLHQbR (ORCPT + 1 other); Fri, 8 Dec 2017 11:31:17 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2230 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754362AbdLHQbH (ORCPT ); Fri, 8 Dec 2017 11:31:07 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id DD99971A7D200; Sat, 9 Dec 2017 00:30:44 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.361.1; Sat, 9 Dec 2017 00:30:39 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 11/19] scsi: hisi_sas: improve int_chnl_int_v2_hw() consistency with v3 hw Date: Sat, 9 Dec 2017 01:16:42 +0800 Message-ID: <1512753410-50924-12-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1512753410-50924-1-git-send-email-john.garry@huawei.com> References: <1512753410-50924-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiaofei Tan Change code format of int_chnl_int_v2_hw() to be consistent with v3 hw to reduce an tag indent. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 58 ++++++++++++++++------------------ 1 file changed, 28 insertions(+), 30 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 8d6886a..4c4a000 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -2848,40 +2848,38 @@ static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff; while (irq_msk) { - if (irq_msk & (1 << phy_no)) { - u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, - CHL_INT0); - u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, - CHL_INT1); - u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, - CHL_INT2); - - if (irq_value1) { - if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK | - CHL_INT1_DMAC_TX_ECC_ERR_MSK)) - panic("%s: DMAC RX/TX ecc bad error!\ - (0x%x)", - dev_name(dev), irq_value1); - - hisi_sas_phy_write32(hisi_hba, phy_no, - CHL_INT1, irq_value1); - } + u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, + CHL_INT0); + u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, + CHL_INT1); + u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, + CHL_INT2); + + if ((irq_msk & (1 << phy_no)) && irq_value1) { + if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK | + CHL_INT1_DMAC_TX_ECC_ERR_MSK)) + panic("%s: DMAC RX/TX ecc bad error!\ + (0x%x)", + dev_name(dev), irq_value1); - if (irq_value2) - hisi_sas_phy_write32(hisi_hba, phy_no, - CHL_INT2, irq_value2); + hisi_sas_phy_write32(hisi_hba, phy_no, + CHL_INT1, irq_value1); + } + if ((irq_msk & (1 << phy_no)) && irq_value2) + hisi_sas_phy_write32(hisi_hba, phy_no, + CHL_INT2, irq_value2); - if (irq_value0) { - if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK) - phy_bcast_v2_hw(phy_no, hisi_hba); - hisi_sas_phy_write32(hisi_hba, phy_no, - CHL_INT0, irq_value0 - & (~CHL_INT0_HOTPLUG_TOUT_MSK) - & (~CHL_INT0_SL_PHY_ENABLE_MSK) - & (~CHL_INT0_NOT_RDY_MSK)); - } + if ((irq_msk & (1 << phy_no)) && irq_value0) { + if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK) + phy_bcast_v2_hw(phy_no, hisi_hba); + + hisi_sas_phy_write32(hisi_hba, phy_no, + CHL_INT0, irq_value0 + & (~CHL_INT0_HOTPLUG_TOUT_MSK) + & (~CHL_INT0_SL_PHY_ENABLE_MSK) + & (~CHL_INT0_NOT_RDY_MSK)); } irq_msk &= ~(1 << phy_no); phy_no++;