From patchwork Mon Oct 26 14:14:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 55564 Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp1226668lbq; Mon, 26 Oct 2015 07:12:08 -0700 (PDT) X-Received: by 10.68.201.200 with SMTP id kc8mr22193908pbc.18.1445868727361; Mon, 26 Oct 2015 07:12:07 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w5si53468608pbs.85.2015.10.26.07.12.07 for ; Mon, 26 Oct 2015 07:12:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932341AbbJZOMG (ORCPT ); Mon, 26 Oct 2015 10:12:06 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:6698 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754455AbbJZOBr (ORCPT ); Mon, 26 Oct 2015 10:01:47 -0400 Received: from 172.24.1.47 (EHLO szxeml430-hub.china.huawei.com) ([172.24.1.47]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BPR32600; Mon, 26 Oct 2015 22:01:41 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by szxeml430-hub.china.huawei.com (10.82.67.185) with Microsoft SMTP Server id 14.3.235.1; Mon, 26 Oct 2015 22:01:24 +0800 From: John Garry To: , , , , , , CC: , , , , , , , , John Garry Subject: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS Date: Mon, 26 Oct 2015 22:14:33 +0800 Message-ID: <1445868903-183817-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445868903-183817-1-git-send-email-john.garry@huawei.com> References: <1445868903-183817-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.562E3245.0328, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: dc4f52816f482ae89980f8a44a2f4a28 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Add devicetree bindings for HiSilicon SAS driver. Signed-off-by: John Garry --- .../devicetree/bindings/scsi/hisilicon-sas.txt | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt new file mode 100644 index 0000000..d1e7b2a --- /dev/null +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt @@ -0,0 +1,70 @@ +* HiSilicon SAS controller + +The HiSilicon SAS controller supports SAS/SATA. + +Main node required properties: + - compatible : value should be as follows: + (a) "hisilicon,sas-controller-v1" for v1 of HiSilicon SAS controller IP + - reg : Address and length of the SAS register + - hisilicon,sas-syscon: phandle of syscon used for sas control + - ctrl-reg : offset to the following SAS control registers (in order): + - reset assert + - clock disable + - reset status + - reset de-assert + - clock enable + - queue-count : number of delivery and completion queues in the controller + - phy-count : number of phys accessible by the controller + - interrupts : Interrupts for phys, completion queues, and fatal + interrupts: + - Each phy has 3 interrupt sources: + - broadcast + - phyup + - abnormal + - Each completion queue has 1 interrupt source + - Each controller has 2 fatal interrupt sources: + - ECC + - AXI bus + +* HiSilicon SAS syscon + +Required properties: +- compatible: should be "hisilicon,sas-ctrl", "syscon" +- reg: offset and length of the syscon sas-ctrl registers + + +Example: + sas_ctrl0: sas_ctrl@c0000000 { + compatible = "hisilicon,sas-ctrl", "syscon"; + reg = <0x0 0xc0000000 0x0 0x10000>; + }; + + sas0: sas@c1000000 { + compatible = "hisilicon,sas-controller-v1"; + reg = <0x0 0xc1000000 0x0 0x10000>; + hisilicon,sas-syscon = <&sas_ctrl0>; + ctrl-reg = <0xa60 0x33c 0x5a30 0xa64 0x338>; + queue-count = <32>; + phy-count = <8>; + dma-coherent; + interrupt-parent = <&mbigen_dsa>; + interrupts = <259 4>, <263 4>,<264 4>,/* phy irq(0~79) */ + <269 4>,<273 4>,<274 4>,/* phy irq(0~79) */ + <279 4>,<283 4>,<284 4>,/* phy irq(0~79) */ + <289 4>,<293 4>,<294 4>,/* phy irq(0~79) */ + <299 4>,<303 4>,<304 4>,/* phy irq(0~79) */ + <309 4>,<313 4>,<314 4>,/* phy irq(0~79) */ + <319 4>,<323 4>,<324 4>,/* phy irq(0~79) */ + <329 4>,<333 4>,<334 4>,/* phy irq(0~79) */ + <336 1>,<337 1>,<338 1>,<339 1>,<340 1>, + <341 1>,<342 1>,<343 1>,/* cq irq (80~111) */ + <344 1>,<345 1>,<346 1>,<347 1>,<348 1>, + <349 1>,<350 1>,<351 1>,/* cq irq (80~111) */ + <352 1>,<353 1>,<354 1>,<355 1>,<356 1>, + <357 1>,<358 1>,<359 1>,/* cq irq (80~111) */ + <360 1>,<361 1>,<362 1>,<363 1>,<364 1>, + <365 1>,<366 1>,<367 1>,/* cq irq (80~111) */ + <376 4>,/* chip fatal error irq(120) */ + <381 4>;/* chip fatal error irq(125) */ + status = "disabled"; + };