From patchwork Wed Jul 29 13:47:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Tucker X-Patchwork-Id: 247249 Delivered-To: patch@linaro.org Received: by 2002:a50:110d:0:0:0:0:0 with SMTP id e13csp1126039eck; Wed, 29 Jul 2020 06:47:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzT6OiM+YQhrYCKnTxuYCM66RmHQiHvOv6l+Ul5SxAdDC6Oitb2gQMiF9eOyg7J4I0rLRhJ X-Received: by 2002:a17:906:5812:: with SMTP id m18mr6573187ejq.66.1596030475003; Wed, 29 Jul 2020 06:47:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596030474; cv=none; d=google.com; s=arc-20160816; b=NAUx+S4jyus/8Evy4SkDAqf9KA/DZMOWOuolQmyl949bbt1oVeiSEMwUz4/0U/oa37 MdFGIXmwvZO+GBPynhYpRMeg7Z0Z+u3eiY2UBmhRAbRGbRosQ8ozpP+uyu7unHVsCNo3 VAOekKE2dSCdg/WoGQDwTnJOpJoiiXfmbh7OTCiv6pQDFb1TKyryRLxSI6r+71FlWL22 qn08XIJyNU68dgD+/blfbCsT5Z7X5+s3pI02QaSZJafaZf0jPabAVy8f/lp6ULW+iQvZ s9t1IDyRCjEjdfdrSTc+5nWXwPglA2iI86LeDuR/jL13mG3TltSq6OgPdOhl2OcxnrQD syIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ndSo0UzCfCde4A2SjLjEseiYtNQq+J4eSVI1kJzsPf4=; b=Laj86c05aINn4CNg0qrfvDrfscoXyXHFVuctUljhl5kIEHYPoopAW40p8EtxBWJ78H 1VP2T78j3jk8MHp5GJ6KXQs5P8NdpYI/HJ+xEv1zL0rfEZZJnWSPD3jNB7tF/BT9Wiy2 8qKrB/1Hqusx/65c5odFC9GQpMiFYAEyLLZAOAEtldT03OYaYMSzrob/2AmscbHX4oDH Yz1MQYt/CJiu91/2KF6Qt4ybSS1AGyvOXEBFrM+NFmrPGzP34Y+DdW5Ytsd6NMIJdUI2 T5o08SYyeAfhxHM0U2eBmcIrP3/H/nvg7hnBX41E3Tilxh/EIgIM4wsOJRH7QvS5BYGU egVg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e19si1242001edv.165.2020.07.29.06.47.54; Wed, 29 Jul 2020 06:47:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726813AbgG2Nrx (ORCPT + 4 others); Wed, 29 Jul 2020 09:47:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726336AbgG2Nrw (ORCPT ); Wed, 29 Jul 2020 09:47:52 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94D9CC061794; Wed, 29 Jul 2020 06:47:52 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: gtucker) with ESMTPSA id BF029298182 From: Guillaume Tucker To: Russell King , Kukjin Kim , Krzysztof Kozlowski , Rob Herring Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] ARM: l2c: update prefetch bits in L2X0_AUX_CTRL using DT value Date: Wed, 29 Jul 2020 14:47:32 +0100 Message-Id: <79a628daef56c2d542e379f550de21da4fe3c901.1596028601.git.guillaume.tucker@collabora.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <860eb8a1eed879e55daf960c96acdac514cbda93.1596028601.git.guillaume.tucker@collabora.com> References: <860eb8a1eed879e55daf960c96acdac514cbda93.1596028601.git.guillaume.tucker@collabora.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The L310_PREFETCH_CTRL register bits 28 and 29 to enable data and instruction prefetch respectively can also be accessed via the L2X0_AUX_CTRL register. They appear to be actually wired together in hardware between the registers. Changing them in the prefetch register only will get undone when restoring the aux control register later on. For this reason, set these bits in both registers during initialisation according to the DT attributes. Fixes: ec3bd0e68a67 ("ARM: 8391/1: l2c: add options to overwrite prefetching behavior") Signed-off-by: Guillaume Tucker --- arch/arm/mm/cache-l2x0.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 12c26eb88afb..43d91bfd2360 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1249,20 +1249,28 @@ static void __init l2c310_of_parse(const struct device_node *np, ret = of_property_read_u32(np, "prefetch-data", &val); if (ret == 0) { - if (val) + if (val) { prefetch |= L310_PREFETCH_CTRL_DATA_PREFETCH; - else + *aux_val |= L310_PREFETCH_CTRL_DATA_PREFETCH; + } else { prefetch &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; + *aux_val &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; + } + *aux_mask &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; } else if (ret != -EINVAL) { pr_err("L2C-310 OF prefetch-data property value is missing\n"); } ret = of_property_read_u32(np, "prefetch-instr", &val); if (ret == 0) { - if (val) + if (val) { prefetch |= L310_PREFETCH_CTRL_INSTR_PREFETCH; - else + *aux_val |= L310_PREFETCH_CTRL_INSTR_PREFETCH; + } else { prefetch &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; + *aux_val &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; + } + *aux_mask &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; } else if (ret != -EINVAL) { pr_err("L2C-310 OF prefetch-instr property value is missing\n"); }