From patchwork Mon Aug 10 12:22:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Tucker X-Patchwork-Id: 247585 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp4812243ilo; Mon, 10 Aug 2020 05:22:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwC03g+cLMc4rRXus47o4c7KM4uZynGFtGQjOC3x440e9Ml6kcNq1Pp7sNrX8wSzO81kSAo X-Received: by 2002:a17:906:aed4:: with SMTP id me20mr22225681ejb.141.1597062159882; Mon, 10 Aug 2020 05:22:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1597062159; cv=none; d=google.com; s=arc-20160816; b=UpTpk5FmO4gIClP+SNyhMaHrxvLjSdcYYATvgKkXf+C2bpqjSxeif8FSjvHuLnT6ds WvWoaPrtgczbt0jLYk1I/j+fdbwQPm59Lsb68SrXCZH9uxBHQ19ElWaeP0t6V2b3Qlh2 Y93EMZs1tZQ3c6knOGG0jSHUkVT4WLRRURuHOxb7lQYyCmRq00cP1WVErz2jdaPFowOw PLFN3K/iEf1u0kLhD4aHasPFvmDGXywfF0VZZHHKImTJCcI0qagmkmqW2HYWsnrEhfyR VScYnEZ5l2gbX9IHNiTQi5zAGyjZ/MzwvpnwwKOONnsK/jUcdOQNZ7C34aVjqzh9uHCA HzyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=fAdSfzG7uN6HaaXIR2r+Lu8Bn00p1frkARkXnJX1jiU=; b=sSDQc/NUn9NyuqBHcEDt7yPOGOLsSM32tfNgZhgCEo+z8y8jE6vLIK77WjiLOsqyU8 sttDvg2m8ArtkJGVaWQFx8txdik22hhmJqr1DoUJTGPF53b0ynXV5l9/TG4UGHUUexfc IHqj23suttGlfvSGEqJq8QcVw/X2eCwsDBxWWDP4jThM8Z4jSZCGO2fmjHNIV7BCmSjq yu+AgEdhHxsrP7nTQ3g+tdAWsXORyc6lJaWdiJ/E0GxLxRwquB7/40aAOuShL7I4XTTk syy7cDq1LKSars5kltY1Ynvr74DGdsVX/W+vtx7jkMdGMeZHw2hvAp3caEZSptSKWsZn SgSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k24si8956818eds.441.2020.08.10.05.22.39; Mon, 10 Aug 2020 05:22:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726632AbgHJMW0 (ORCPT + 4 others); Mon, 10 Aug 2020 08:22:26 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:45656 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726141AbgHJMW0 (ORCPT ); Mon, 10 Aug 2020 08:22:26 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: gtucker) with ESMTPSA id 72289293506 From: Guillaume Tucker To: Russell King , Kukjin Kim , Krzysztof Kozlowski , Rob Herring Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] ARM: l2c: fix prefetch bits init in L2X0_AUX_CTRL using DT values Date: Mon, 10 Aug 2020 13:22:06 +0100 Message-Id: <76f2f3ad5e77e356e0a5b99ceee1e774a2842c25.1597061474.git.guillaume.tucker@collabora.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <267a81e550a0b5d479c82b5908e2a2caa4c9c874.1597061474.git.guillaume.tucker@collabora.com> References: <267a81e550a0b5d479c82b5908e2a2caa4c9c874.1597061474.git.guillaume.tucker@collabora.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The L310_PREFETCH_CTRL register bits 28 and 29 to enable data and instruction prefetch respectively can also be accessed via the L2X0_AUX_CTRL register. They appear to be actually wired together in hardware between the registers. Changing them in the prefetch register only will get undone when restoring the aux control register later on. For this reason, set these bits in both registers during initialisation according to the devicetree property values. Fixes: ec3bd0e68a67 ("ARM: 8391/1: l2c: add options to overwrite prefetching behavior") Signed-off-by: Guillaume Tucker --- Notes: v2: tweak commit message to show this is a fix arch/arm/mm/cache-l2x0.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 12c26eb88afb..43d91bfd2360 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1249,20 +1249,28 @@ static void __init l2c310_of_parse(const struct device_node *np, ret = of_property_read_u32(np, "prefetch-data", &val); if (ret == 0) { - if (val) + if (val) { prefetch |= L310_PREFETCH_CTRL_DATA_PREFETCH; - else + *aux_val |= L310_PREFETCH_CTRL_DATA_PREFETCH; + } else { prefetch &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; + *aux_val &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; + } + *aux_mask &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; } else if (ret != -EINVAL) { pr_err("L2C-310 OF prefetch-data property value is missing\n"); } ret = of_property_read_u32(np, "prefetch-instr", &val); if (ret == 0) { - if (val) + if (val) { prefetch |= L310_PREFETCH_CTRL_INSTR_PREFETCH; - else + *aux_val |= L310_PREFETCH_CTRL_INSTR_PREFETCH; + } else { prefetch &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; + *aux_val &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; + } + *aux_mask &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; } else if (ret != -EINVAL) { pr_err("L2C-310 OF prefetch-instr property value is missing\n"); }