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Wed, 23 Apr 2025 04:41:59 +0000 (GMT) Received: from epsmgmc1p1new.samsung.com (unknown [182.195.42.40]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20250423044159epsmtrp2256fdcb9d71d512aee46cd285469b31f~42OG10lfz0544505445epsmtrp2N; Wed, 23 Apr 2025 04:41:59 +0000 (GMT) X-AuditID: b6c32a28-460ee70000001e8a-0e-68086f97861e Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmc1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 04.48.07818.79F68086; Wed, 23 Apr 2025 13:41:59 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.60]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250423044159epsmtip1d13252d2ffa850de0665b63f037a8aa4~42OGgaocV1228512285epsmtip1c; Wed, 23 Apr 2025 04:41:59 +0000 (GMT) From: Shin Son To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Sunyeal Hong Cc: Shin Son , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: clock: exynosautov920: add cpucl0 clock definitions Date: Wed, 23 Apr 2025 13:41:51 +0900 Message-ID: <20250423044153.1288077-2-shin.son@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250423044153.1288077-1-shin.son@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNLMWRmVeSWpSXmKPExsWy7bCSnO70fI4Mg9sbxS0ezNvGZrFm7zkm i+tfnrNazD9yjtXi/PkN7BabHl9jtfjYc4/V4vKuOWwWM87vY7K4eMrV4v+eHewWh9+0s1r8 u7aRxWLy8bWsFk3L1jM58Hu8v9HK7rFpVSebx+Yl9R59W1YxenzeJBfAGsVlk5Kak1mWWqRv l8CVsffcJ5aCqxIVEzeGNDAuF+5i5OSQEDCR2N98mKWLkYtDSGA3o0T7mQZGiISExOEZE6Bs YYn7LUdYIYreM0r0dK0G6uDgYBNQldj0Wx4kLiLwlkli+f8DTCANzAKnGSV2npEBsYUFIiQO 3ACp5+RgAarvmbqTFcTmFbCWOLDvGivIHAkBeYn+DgmQMKeAjcTMhl1ge4WASiYv+cIGUS4o cXLmExaI8fISzVtnM09gFJiFJDULSWoBI9MqRsnUguLc9NxkwwLDvNRyveLE3OLSvHS95Pzc TYzg+NDS2MH47luT/iFGJg7GQ4wSHMxKIry/3NgzhHhTEiurUovy44tKc1KLDzFKc7AoifOu NIxIFxJITyxJzU5NLUgtgskycXBKNTAFzFnTFFdV0XM7udvBomTlrl6t6GtPbx1N97tka/Bt botFzYrLVl/K5fwT4l9+jFyTIXRqedIG4fPcGola9ZPLrSMZFj7/YdX2ZcNJWY+lN9bxnXQ8 eS3GuOT+rVleu9vU5gsfKnp24m2nCb+vd+iTH/u6d4kHsKxxaLnzysOt6eXfCaszTx+ynnDh 7rX7Ndm/002nHdF51/98drbv2xCdcPXs0PY/Dyu5q/RDDE/+4ZN+cK2u8/PeI4sibeeILvq8 a//yF4Fud55sO+g5S1vGv2mTgtzlBYYbhR8tecnGXPh6dc1G/geTzHwSlklZ2FZtZ0yQqNS9 uGDe2ktf33Nukuk1e3LMyWR3s4tql98lJZbijERDLeai4kQAceVmyf4CAAA= X-CMS-MailID: 20250423044159epcas2p26a4d07552b5646c7e076f3989d8ea354 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250423044159epcas2p26a4d07552b5646c7e076f3989d8ea354 References: <20250423044153.1288077-1-shin.son@samsung.com> Add cpucl0 clock definitions. CPUCL0 refers to CPU Cluster 0, which provide clock support for the CPUs on Exynosauto V920 SoC. Signed-off-by: Shin Son --- .../clock/samsung,exynosautov920-clock.yaml | 25 +++++++++++++++++++ .../clock/samsung,exynosautov920.h | 19 ++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml index 3330b2727474..d12b17c177df 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml @@ -8,6 +8,7 @@ title: Samsung ExynosAuto v920 SoC clock controller maintainers: - Sunyeal Hong + - Shin Son - Chanwoo Choi - Krzysztof Kozlowski - Sylwester Nawrocki @@ -32,6 +33,7 @@ properties: compatible: enum: - samsung,exynosautov920-cmu-top + - samsung,exynosautov920-cmu-cpucl0 - samsung,exynosautov920-cmu-peric0 - samsung,exynosautov920-cmu-peric1 - samsung,exynosautov920-cmu-misc @@ -69,6 +71,29 @@ allOf: items: - const: oscclk + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl0 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL0 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP) + - description: CMU_CPUCL0 DBG clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + - const: dbg + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h index 0c681f2ba3d0..c57a1d749700 100644 --- a/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -162,6 +162,25 @@ #define DOUT_CLKCMU_TAA_NOC 146 #define DOUT_TCXO_DIV2 147 +/* CMU_CPUCL0 */ +#define CLK_FOUT_CPUCL0_PLL 1 + +#define CLK_MOUT_PLL_CPUCL0 2 +#define CLK_MOUT_CPUCL0_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL0_DBG_USER 4 +#define CLK_MOUT_CPUCL0_SWITCH_USER 5 +#define CLK_MOUT_CPUCL0_CLUSTER 6 +#define CLK_MOUT_CPUCL0_CORE 7 + +#define CLK_DOUT_CLUSTER0_ACLK 8 +#define CLK_DOUT_CLUSTER0_ATCLK 9 +#define CLK_DOUT_CLUSTER0_MPCLK 10 +#define CLK_DOUT_CLUSTER0_PCLK 11 +#define CLK_DOUT_CLUSTER0_PERIPHCLK 12 +#define CLK_DOUT_CPUCL0_DBG_NOC 13 +#define CLK_DOUT_CPUCL0_DBG_PCLKDBG 14 +#define CLK_DOUT_CPUCL0_NOCP 15 + /* CMU_PERIC0 */ #define CLK_MOUT_PERIC0_IP_USER 1 #define CLK_MOUT_PERIC0_NOC_USER 2