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([94.131.202.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43661219a7csm513321455e9.24.2025.01.04.08.43.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jan 2025 08:43:27 -0800 (PST) From: Ivaylo Ivanov To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] arm64: dts: exynos8895: add syscon nodes for peric0/1 and fsys0/1 Date: Sat, 4 Jan 2025 18:43:17 +0200 Message-ID: <20250104164321.333669-3-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250104164321.333669-1-ivo.ivanov.ivanov1@gmail.com> References: <20250104164321.333669-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add syscon nodes for peric0/1, typically used for USI, and fsys0/1, typically used for PCI. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index 4fb9be850..5302a8c1b 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -228,6 +228,12 @@ cmu_peric0: clock-controller@10400000 { "usi1", "usi2", "usi3"; }; + syscon_peric0: syscon@10420000 { + compatible = "samsung,exynos8895-peric0-sysreg", "syscon"; + reg = <0x10420000 0x2000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; + }; + serial_0: serial@10430000 { compatible = "samsung,exynos8895-uart"; reg = <0x10430000 0x100>; @@ -273,6 +279,12 @@ cmu_peric1: clock-controller@10800000 { "usi10", "usi11", "usi12", "usi13"; }; + syscon_peric1: syscon@10820000 { + compatible = "samsung,exynos8895-peric1-sysreg", "syscon"; + reg = <0x10820000 0x2000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; + }; + serial_1: serial@10830000 { compatible = "samsung,exynos8895-uart"; reg = <0x10830000 0x100>; @@ -380,6 +392,12 @@ cmu_fsys0: clock-controller@11000000 { "ufs", "usbdrd30"; }; + syscon_fsys0: syscon@11020000 { + compatible = "samsung,exynos8895-fsys0-sysreg", "syscon"; + reg = <0x11020000 0x2000>; + clocks = <&cmu_fsys0 CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK>; + }; + pinctrl_fsys0: pinctrl@11050000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x11050000 0x1000>; @@ -398,6 +416,12 @@ cmu_fsys1: clock-controller@11400000 { clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; }; + syscon_fsys1: syscon@11420000 { + compatible = "samsung,exynos8895-fsys1-sysreg", "syscon"; + reg = <0x11420000 0x2000>; + clocks = <&cmu_fsys1 CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK>; + }; + pinctrl_fsys1: pinctrl@11430000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x11430000 0x1000>;