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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b339612sm693762966b.84.2024.11.27.03.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Nov 2024 03:01:42 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 27 Nov 2024 11:01:42 +0000 Subject: [PATCH 4/6] arm64: dts: exynos: gs101: enable snps,dis_rxdet_inp3_quirk for DWC3 Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241127-gs101-phy-lanes-orientation-dts-v1-4-5222d8508b71@linaro.org> References: <20241127-gs101-phy-lanes-orientation-dts-v1-0-5222d8508b71@linaro.org> In-Reply-To: <20241127-gs101-phy-lanes-orientation-dts-v1-0-5222d8508b71@linaro.org> To: Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagan Sridharan , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?A?= =?utf-8?q?ndr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 This is required for the DWC3 core to reliably detect the connected phy's Vbus state. Signed-off-by: André Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 18d4e7852a1a..ab016fe9b99a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1302,6 +1302,7 @@ usbdrd31_dwc3: usb@0 { interrupts = ; phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; phy-names = "usb2-phy", "usb3-phy"; + snps,dis_rxdet_inp3_quirk; status = "disabled"; }; };