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[83.25.114.69]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7acab23d56sm58342066b.38.2024.07.25.03.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jul 2024 03:40:47 -0700 (PDT) From: Artur Weber Date: Thu, 25 Jul 2024 12:40:38 +0200 Subject: [PATCH v2 4/6] ARM: dts: samsung: exynos4212-tab3: Add MCLK2 clock to WM1811 codec config Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-midas-audio-tab3-v2-4-dbc055c27879@gmail.com> References: <20240725-midas-audio-tab3-v2-0-dbc055c27879@gmail.com> In-Reply-To: <20240725-midas-audio-tab3-v2-0-dbc055c27879@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1158; i=aweber.kernel@gmail.com; h=from:subject:message-id; bh=jHWT0Fa+xhOf6Fte2P6lvkJ4mgTfM/iqD1caxnjhtGk=; b=owEBbQKS/ZANAwAKAbO7+KEToFFoAcsmYgBmoiuo/j+1OWobQ2BFtLgRwLTmCNNfv8vZtkvJq eWwbWcRkhWJAjMEAAEKAB0WIQTmYwAOrB3szWrSiQ2zu/ihE6BRaAUCZqIrqAAKCRCzu/ihE6BR aHJiEACOfWoLCfrTTHzQfVC3ppsNF4bl/G0huge1xId4KARL7Pl6fDS/9LsgEP2BZ/nRv+lCzpH TYb/bcPcAEsxLV0VfJBGf1Kh0Ql9Zy0k6qgOv4Ody+XdxV8JFL9EDw/cH3q/1Jo34oaFF2X4nm/ PfDvK//aK6sGVYvLc5Fan0tt2fhRFnfzvKt+4SGHoyQC7q1Mym30YSF2kfHNQa4og7jNQOl8OaA 3eR7To3EdzZvjOGOSJaIcUYdyOgsUXZAjOBuRHlP8SeHsnBynmpvqBTSkkBsgHxh17rgkZZaWe/ HL+Uyzuxi8M9XfMc6DnJYB9LMtFS0Bszhkpob0z8zaqrRssEV+Zl3kherkqk3V0uHkUU7Xf/XYX WdJv097bim0r5mKdon/UQLYvXnsIPukB/opj9ld6JX7vTLEuugtML/Vp+t19EUgC1dycBhJU2Gs Qo2J4oUXWx1/9i5VAkqJ0WYjFjjiA6403criZcbK68QEmwzv1WdCP0+HfSD4kTS67mwZm3YVulX +oH3g6i3EXv+owUSaHCjoPK3EwOor6gia4U13ZZC8FUqGj4XlQYlLYFQ2t6rbCvKY8RyJXoMJ+3 DjYJ/5T6umwtK9jnWtG8NidAjNDR84BKQkuC6YJ1+C1W5NiJkyY1/vhOOsV03b6fUY0SbW4AHK5 MWTK3+xkVk4sRhg== X-Developer-Key: i=aweber.kernel@gmail.com; a=openpgp; fpr=E663000EAC1DECCD6AD2890DB3BBF8A113A05168 In the schematics, the MCLK2 pin is shown as connected to CODEC_CLK32K, which is derived from the same 32KHZ_PMIC clock as Bluetooth/WiFi and GPS clocks. 32KHZ_PMIC is connected to the BTCLK pin, represented in mainline as S2MPS11_CLK_BT. Add the MCLK2 clock to the WM1811 codec clock property to properly describe the hardware. Signed-off-by: Artur Weber --- arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi index bbafd4ece5f7..5106bb752b7d 100644 --- a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi @@ -535,8 +535,9 @@ &i2c_4 { wm1811: audio-codec@1a { compatible = "wlf,wm1811"; reg = <0x1a>; - clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; + clocks = <&pmu_system_controller 0>, + <&s5m8767_osc S2MPS11_CLK_BT>; + clock-names = "MCLK1", "MCLK2"; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&gpx3>;