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[83.8.128.191]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626cc500a1sm798430166b.125.2024.05.30.01.56.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 01:56:30 -0700 (PDT) From: Artur Weber Date: Thu, 30 May 2024 10:55:54 +0200 Subject: [PATCH RFC 04/11] mfd: max77693: Add defines for OTG control Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240530-max77693-charger-extcon-v1-4-dc2a9e5bdf30@gmail.com> References: <20240530-max77693-charger-extcon-v1-0-dc2a9e5bdf30@gmail.com> In-Reply-To: <20240530-max77693-charger-extcon-v1-0-dc2a9e5bdf30@gmail.com> To: Krzysztof Kozlowski , Chanwoo Choi Cc: Sebastian Reichel , Rob Herring , Conor Dooley , Lee Jones , Krzysztof Kozlowski , Alim Akhtar , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Henrik Grimler , Wolfgang Wiedmeyer , Denis 'GNUtoo' Carikli , Artur Weber X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717059384; l=880; i=aweber.kernel@gmail.com; s=20231030; h=from:subject:message-id; bh=fdFCdouFtABSDklI2okYjmv8ltu44PsbFfLaKdFasJM=; b=8aX85TIyQjQICfocT2JKEutODUeUhtAi6tDWjBrIvXV+CLc35vHCgMqCX6obQhvgLowcjr6wS xa0Bz58phthB5z7BfcbkPIzTsiXTRMm/UD8Ml2DTD9NspcfNzLJPJu8 X-Developer-Key: i=aweber.kernel@gmail.com; a=ed25519; pk=RhDBfWbJEHqDibXbhNEBAnc9FMkyznGxX/hwfhL8bv8= These three bits are used to enable OTG control in the charger driver. Add them in preparation for an updated driver. Signed-off-by: Artur Weber --- include/linux/mfd/max77693-private.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h index 4570646e2f33..4448b024255d 100644 --- a/include/linux/mfd/max77693-private.h +++ b/include/linux/mfd/max77693-private.h @@ -209,7 +209,10 @@ enum max77693_charger_battery_state { /* MAX77693 CHG_CNFG_00 register */ #define CHG_CNFG_00_CHG_MASK 0x1 +#define CHG_CNFG_00_OTG_MASK 0x2 #define CHG_CNFG_00_BUCK_MASK 0x4 +#define CHG_CNFG_00_BOOST_MASK 0x8 +#define CHG_CNFG_00_DIS_MUIC_CTRL_MASK 0x20 /* MAX77693_CHG_REG_CHG_CNFG_01 register */ #define CHG_CNFG_01_FCHGTIME_SHIFT 0