| Message ID | 20240503151129.3901815-12-l.stach@pengutronix.de |
|---|---|
| State | New |
| Headers | show |
| Series | improve Analogix DP AUX channel handling | expand |
On Fri, May 3, 2024 at 5:12 PM Lucas Stach <l.stach@pengutronix.de> wrote: > > The PLL will be reconfigured later, which may cause it to go out of lock > anyways, so there is no point in waiting for the PLL to lock here. Instead > we can continue execution of the link setup, which will properly set the > PLL parameters and will wait for the PLL to lock at the appropriate times. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 14 +------------- > 1 file changed, 1 insertion(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > index d267cf05cbca..e9c643a8b6fc 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > @@ -356,7 +356,6 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, > int analogix_dp_init_analog_func(struct analogix_dp_device *dp) > { > u32 reg; > - int timeout_loop = 0; > > analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); > > @@ -368,18 +367,7 @@ int analogix_dp_init_analog_func(struct analogix_dp_device *dp) > writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); > > /* Power up PLL */ > - if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { > - analogix_dp_set_pll_power_down(dp, 0); > - > - while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { > - timeout_loop++; > - if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { > - dev_err(dp->dev, "failed to get pll lock status\n"); > - return -ETIMEDOUT; > - } > - usleep_range(10, 20); > - } > - } > + analogix_dp_set_pll_power_down(dp, 0); > > /* Enable Serdes FIFO function and Link symbol clock domain module */ > reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); > -- > 2.39.2 > Reviewed-by: Robert Foss <rfoss@kernel.org>
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c index d267cf05cbca..e9c643a8b6fc 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -356,7 +356,6 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, int analogix_dp_init_analog_func(struct analogix_dp_device *dp) { u32 reg; - int timeout_loop = 0; analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); @@ -368,18 +367,7 @@ int analogix_dp_init_analog_func(struct analogix_dp_device *dp) writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); /* Power up PLL */ - if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { - analogix_dp_set_pll_power_down(dp, 0); - - while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { - timeout_loop++; - if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { - dev_err(dp->dev, "failed to get pll lock status\n"); - return -ETIMEDOUT; - } - usleep_range(10, 20); - } - } + analogix_dp_set_pll_power_down(dp, 0); /* Enable Serdes FIFO function and Link symbol clock domain module */ reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
The PLL will be reconfigured later, which may cause it to go out of lock anyways, so there is no point in waiting for the PLL to lock here. Instead we can continue execution of the link setup, which will properly set the PLL parameters and will wait for the PLL to lock at the appropriate times. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-)