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AJvYcCWPqWDban1QTwg8SxAulTcYALqQVjTEXuQJgz+FV7alBR028TFDqq9upWCPCx3SviFshFXl3HseKT5n28mIctLU4ToEzD8EgjYZjVMQyucBFf0= X-Gm-Message-State: AOJu0Yz+t702dTuRm9jg3xWZLi6GJkDnaw5bXazFqtJ0uHmjYBeud3Hk aimbvNk0bHTaTY5iqtAQkhlnf7dJr9TQ6VAxw2PitDX7BJFnLiZUCYF7pDKKgAg= X-Google-Smtp-Source: AGHT+IFPwolxzCboIWuNQSJZ2XhYWLaaMBqWMqD+P8Hwf2SoPTkZkMnz+PbJcqdGhuszLk7XVCKSZg== X-Received: by 2002:a5d:6a8a:0:b0:34b:e446:3e0 with SMTP id s10-20020a5d6a8a000000b0034be44603e0mr1814853wru.47.1714134016110; Fri, 26 Apr 2024 05:20:16 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:63cc:9bae:f542:50e4]) by smtp.gmail.com with ESMTPSA id q2-20020adff942000000b00346bda84bf9sm22478146wrr.78.2024.04.26.05.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 05:20:15 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski Subject: [PATCH v3 5/6] scsi: ufs: host: ufs-exynos: add some pa_dbg_ register offsets into drvdata Date: Fri, 26 Apr 2024 13:20:03 +0100 Message-ID: <20240426122004.2249178-6-peter.griffin@linaro.org> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog In-Reply-To: <20240426122004.2249178-1-peter.griffin@linaro.org> References: <20240426122004.2249178-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This allows these registers to be at different offsets or not exist at all on some SoCs variants. Signed-off-by: Peter Griffin Acked-by: Krzysztof Kozlowski Tested-by: Will McVicker --- drivers/ufs/host/ufs-exynos.c | 38 ++++++++++++++++++++++++----------- drivers/ufs/host/ufs-exynos.h | 6 +++++- 2 files changed, 31 insertions(+), 13 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 66093a905986..c086630a96e8 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -308,8 +308,9 @@ static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs, static int exynos7_ufs_pre_link(struct exynos_ufs *ufs) { + struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; + u32 val = attr->pa_dbg_opt_suite1_val; struct ufs_hba *hba = ufs->hba; - u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite; int i; exynos_ufs_enable_ov_tm(hba); @@ -326,12 +327,13 @@ static int exynos7_ufs_pre_link(struct exynos_ufs *ufs) UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); udelay(1); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12)); + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), + val | (1 << 12)); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); udelay(1600); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val); + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val); return 0; } @@ -923,14 +925,19 @@ static int exynos_ufs_phy_init(struct exynos_ufs *ufs) static void exynos_ufs_config_unipro(struct exynos_ufs *ufs) { + struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; struct ufs_hba *hba = ufs->hba; - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD), - DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); + if (attr->pa_dbg_clk_period_off) + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), + DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), ufs->drv_data->uic_attr->tx_trailingclks); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), - ufs->drv_data->uic_attr->pa_dbg_option_suite); + + if (attr->pa_dbg_opt_suite1_off) + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), + attr->pa_dbg_opt_suite1_val); } static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index) @@ -1488,10 +1495,11 @@ static int exynosauto_ufs_vh_init(struct ufs_hba *hba) static int fsd_ufs_pre_link(struct exynos_ufs *ufs) { - int i; + struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; struct ufs_hba *hba = ufs->hba; + int i; - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD), + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12); ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); @@ -1515,7 +1523,9 @@ static int fsd_ufs_pre_link(struct exynos_ufs *ufs) ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), 0x2e820183); + + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), + 0x2e820183); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); exynos_ufs_establish_connt(ufs); @@ -1651,7 +1661,9 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr = { .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), - .pa_dbg_option_suite = 0x30103, + .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, + .pa_dbg_opt_suite1_val = 0x30103, + .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, }; static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = { @@ -1725,7 +1737,9 @@ static struct exynos_ufs_uic_attr fsd_uic_attr = { .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), - .pa_dbg_option_suite = 0x2E820183, + .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, + .pa_dbg_opt_suite1_val = 0x2E820183, + .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, }; static const struct exynos_ufs_drv_data fsd_ufs_drvs = { diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index 7acc13914100..f30423223474 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -145,7 +145,11 @@ struct exynos_ufs_uic_attr { /* Common Attributes */ unsigned int cmn_pwm_clk_ctrl; /* Internal Attributes */ - unsigned int pa_dbg_option_suite; + unsigned int pa_dbg_clk_period_off; + unsigned int pa_dbg_opt_suite1_val; + unsigned int pa_dbg_opt_suite1_off; + unsigned int pa_dbg_opt_suite2_val; + unsigned int pa_dbg_opt_suite2_off; /* Changeable Attributes */ unsigned int rx_adv_fine_gran_sup_en; unsigned int rx_adv_fine_gran_step;