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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:34 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 27/28] spi: s3c64xx: add support for google,gs101-spi Date: Thu, 25 Jan 2024 14:50:05 +0000 Message-ID: <20240125145007.748295-28-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for GS101 SPI. All the SPI nodes on GS101 have 64 bytes FIFOs, infer the FIFO size from the compatible. GS101 allows just 32bit register accesses, otherwise a Serror Interrupt is raised. Do the write reg accesses in 32 bits. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 35a2d5554dfd..e887be6955a0 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1501,6 +1501,18 @@ static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config gs101_spi_port_config = { + .fifosize = 64, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .has_loopback = true, + .use_32bit_io = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct s3c64xx_spi_port_config fsd_spi_port_config = { .fifosize = 64, .rx_lvl_offset = 15, @@ -1556,6 +1568,10 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { .compatible = "samsung,exynosautov9-spi", .data = &exynosautov9_spi_port_config, }, + { + .compatible = "google,gs101-spi", + .data = &gs101_spi_port_config, + }, { .compatible = "tesla,fsd-spi", .data = &fsd_spi_port_config,