From patchwork Wed Mar 8 16:39:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 660939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DA80C6FD1E for ; Wed, 8 Mar 2023 16:41:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229614AbjCHQlN (ORCPT ); Wed, 8 Mar 2023 11:41:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229623AbjCHQlL (ORCPT ); Wed, 8 Mar 2023 11:41:11 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21F90B78A4 for ; Wed, 8 Mar 2023 08:41:10 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id m8-20020a17090a4d8800b002377bced051so3026188pjh.0 for ; Wed, 08 Mar 2023 08:41:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1678293669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UsgY6N6catKRCRfBq6xxwmLwSB7PaDK4tqNXn1E6zOw=; b=EKUzQ+uf2Qr4D2RH7a4R6f7r7LAQRae2J1OTJH2ZhmNisTdUXzKZKtmUvsPNZvXWIl wF0q8v5gBfw1kku7VGfXDWf0oWPJgvBlF/xZl17eOl2xh1U7ZNa2oMvt1QHqvBnVtcwp 6pk1XNfWVu9aWPHnBVGAO2UcLQnd9qNSQd/Po= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678293669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UsgY6N6catKRCRfBq6xxwmLwSB7PaDK4tqNXn1E6zOw=; b=00L5iCZTbuGiZ2xh7cYt6VZnX0WX+BmU9oDvMHeCyt1np02PQYVwnYWJFbuK1CNcgq LQdpJPMk8iVUVRFsHQYklwVVAaQDCFXg6et34ejwMeP8J+kmdnKq7uSKHzVjhJwynlCh rMVcTZ5mllUCSVbPel3f4p8ehA1072rIAbjRodjzbXQeuhOfduc1ePtWd0nmVPE/M++7 003PXPZV6XbNZABn7x0PMVhukxBjVBs0xSn3Vr7mvlXttR5ixJ8G0JL6sC0vILuWDBrz UtX6miZJ6v33jEvW9mIUwxl5ltHVKMII3R4FRD/togvi97wtTCQZ7lbGyX1FBPkhNu+U nqMg== X-Gm-Message-State: AO0yUKUxl3JjV8Vz0eFp9sXeoNT4lQu4fpOjZ6cGx08eaFKhIvtpLqwU jwt1PQ3U/PFUmY03pdG6ihyrGg== X-Google-Smtp-Source: AK7set/gQAe3+o6+VsYiC9qcYya5fmJvkX7EmdiPMEJ9xkJP/megCncb/lLPrMvLCCKP5+9ZHN9f4A== X-Received: by 2002:a17:903:244b:b0:19c:c9da:a62e with SMTP id l11-20020a170903244b00b0019cc9daa62emr22126627pls.54.1678293669560; Wed, 08 Mar 2023 08:41:09 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a8a1:b545:91cc:80b2:f9fe]) by smtp.gmail.com with ESMTPSA id kq3-20020a170903284300b0019b9a075f1fsm10046540plb.80.2023.03.08.08.41.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 08:41:09 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v16 09/16] drm: exynos: dsi: Add atomic_get_input_bus_fmts Date: Wed, 8 Mar 2023 22:09:46 +0530 Message-Id: <20230308163953.28506-10-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308163953.28506-1-jagan@amarulasolutions.com> References: <20230308163953.28506-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Finding the right input bus format throughout the pipeline is hard so add atomic_get_input_bus_fmts callback and initialize with the proper input format from list of supported output formats. This format can be used in pipeline for negotiating bus format between the DSI-end of this bridge and the other component closer to pipeline components. List of Pixel formats are taken from, AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 3.7.4 Pixel formats Table 14. DSI pixel packing formats Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Tested-by: Marek Szyprowski Signed-off-by: Jagan Teki --- Changes for v16: - none Changes for v15: - collect RB from Marek Changes for v12: - update the logic suggested by Marek Changes for v11: - collect RB from Frieder - drop extra line Changes for v10: - none Changes for v9: - added MEDIA_BUS_FMT_FIXED - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt list is unsupported. - added MEDIA_BUS_FMT_YUYV10_1X20, MEDIA_BUS_FMT_YUYV12_1X24 Changes for v8: - added pixel formats supported by NXP AN13573 i.MX 8/RT MIPI DSI/CSI-2 Changes for v7 - v4: - none Changes for v3: - include media-bus-format.h Changes for v2: - none Changes for v1: - new patch drivers/gpu/drm/exynos/exynos_drm_dsi.c | 62 +++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 0c480be5f070..bd3bb8622ca3 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -1466,6 +1467,66 @@ static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, pm_runtime_put_sync(dsi->dev); } +/* + * This pixel output formats list referenced from, + * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 + * 3.7.4 Pixel formats + * Table 14. DSI pixel packing formats + */ +static const u32 exynos_dsi_pixel_output_fmts[] = { + MEDIA_BUS_FMT_YUYV10_1X20, + MEDIA_BUS_FMT_YUYV12_1X24, + MEDIA_BUS_FMT_UYVY8_1X16, + MEDIA_BUS_FMT_RGB101010_1X30, + MEDIA_BUS_FMT_RGB121212_1X36, + MEDIA_BUS_FMT_RGB565_1X16, + MEDIA_BUS_FMT_RGB666_1X18, + MEDIA_BUS_FMT_RGB888_1X24, +}; + +static bool exynos_dsi_pixel_output_fmt_supported(u32 fmt) +{ + int i; + + if (fmt == MEDIA_BUS_FMT_FIXED) + return false; + + for (i = 0; i < ARRAY_SIZE(exynos_dsi_pixel_output_fmts); i++) { + if (exynos_dsi_pixel_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +exynos_dsi_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + if (!exynos_dsi_pixel_output_fmt_supported(output_fmt)) + /* + * Some bridge/display drivers are still not able to pass the + * correct format, so handle those pipelines by falling back + * to the default format till the supported formats finalized. + */ + output_fmt = MEDIA_BUS_FMT_RGB888_1X24; + + input_fmts[0] = output_fmt; + *num_input_fmts = 1; + + return input_fmts; +} + static int exynos_dsi_atomic_check(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, @@ -1514,6 +1575,7 @@ static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_get_input_bus_fmts = exynos_dsi_atomic_get_input_bus_fmts, .atomic_check = exynos_dsi_atomic_check, .atomic_pre_enable = exynos_dsi_atomic_pre_enable, .atomic_enable = exynos_dsi_atomic_enable,