From patchwork Thu Jan 26 14:44:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 647465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0048EC05027 for ; Thu, 26 Jan 2023 14:45:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229642AbjAZOp5 (ORCPT ); Thu, 26 Jan 2023 09:45:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229512AbjAZOp4 (ORCPT ); Thu, 26 Jan 2023 09:45:56 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78B555FFF for ; Thu, 26 Jan 2023 06:45:55 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id z9-20020a17090a468900b00226b6e7aeeaso1921953pjf.1 for ; Thu, 26 Jan 2023 06:45:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fCKziNtWsgASij+dWWGaDpyDhpD6z6/DqCOerXlFmzI=; b=rOfFYHAKORMBAsDbvmhXC9docArZMSXO5NJd6EXpuu1shW8vQGvscEZhSVEO07IhZx plUjpN4BdGz8pHwqSKZ7kyKVi/shAcU8LCO2Uq05OGd7/Yzc2+8jMDg+TOf6tMYMpx9h g/eJydgeYV9eoAnqjNCpa6V93Qjzhd5e40NpM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fCKziNtWsgASij+dWWGaDpyDhpD6z6/DqCOerXlFmzI=; b=5FiyaxJ0Sqfx10fjUpZogdshBKxnIBiYSA8CyI3C1UzPGOHI9MyZoQru1V7HOZp2t3 VCUaC1jEqb6HX7r863hiFcL7GObTPvsMj1amXbQjBrn1NlbaL7Tg7zjBHtR3Rx8Oahb1 N5uDZlxuHEDHrPKEeJZH1bQIO7eNICHSd6UgJzGdOgaBnhqMVgVdUj3z7+wDeGPwKr0g FhxqG68Zt2pWWK5LwrXRfvAVwjPNz+mEUuxp+/UFaiUDv9thq1I1MrA3gfxqmkibmUJZ 7EjTc0dL/Ep8J2vb92NG094B6Kdh0Wm3CYMBIflB+cWGkZnU9HNn1KMlIqcpSge+WzPI 20rA== X-Gm-Message-State: AFqh2krOsNqVO8pWGiWqZdKWvjeH8BLmxAcFFFNvAI/SZEE6yAMK6s7k sdecMNDkevBGswtkq7Tnj5jKUA== X-Google-Smtp-Source: AMrXdXsx8jLbNuwIzpEmJpc94JGEd3SiLRYNoLiyE8CiARZx9DzavPmd2ownQUPZOBWdh1bJiJVcqg== X-Received: by 2002:a05:6a20:8f0d:b0:a3:6f97:e658 with SMTP id b13-20020a056a208f0d00b000a36f97e658mr50988661pzk.58.1674744354967; Thu, 26 Jan 2023 06:45:54 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a238:3cb1:2156:ef87:8af5]) by smtp.gmail.com with ESMTPSA id d197-20020a6336ce000000b0042988a04bfdsm823660pga.9.2023.01.26.06.45.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 06:45:54 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Robert Foss , Laurent Pinchart , Marek Vasut Cc: Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP Linux Team , linux-amarula , Jagan Teki Subject: [PATCH v12 06/18] drm: exynos: dsi: Add platform PLL_P (PMS_P) offset Date: Thu, 26 Jan 2023 20:14:15 +0530 Message-Id: <20230126144427.607098-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230126144427.607098-1-jagan@amarulasolutions.com> References: <20230126144427.607098-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Look like PLL PMS_P offset value varies between platforms that have Samsung DSIM IP. However, there is no clear evidence for it as both Exynos and i.MX 8M Mini Application Processor Reference Manual is still referring the PMS_P offset as 13. The offset 13 is not working for i.MX8M Mini SoCs but the downstream NXP sec-dsim.c driver is using offset 14 for i.MX8M Mini SoC platforms [1] [2]. PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P() with offset 13 and then an additional offset of one bit added in sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS(). Not sure whether it is reference manual documentation or something else but this patch trusts the downstream code and handle PLL_P offset via platform driver data so-that imx8mm driver data shall use pll_p_offset to 14. Similar to Mini the i.MX8M Nano/Plus also has P=14, unlike Exynos. [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n210 [2] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211 Reviewed-by: Marek Vasut Signed-off-by: Frieder Schrempf Signed-off-by: Jagan Teki --- Changes for v12, v11, v10, v9: - none Changes for v8: - updated commit message for 8M Nano/Plus Changes for v7, v6: - none Changes for v5: - updated clear commit message Changes for v4, v3, v2: - none Changes for v1: - updated commit message - add downstream driver link drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 5918d31127aa..7a845badb1b2 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -194,7 +194,7 @@ /* DSIM_PLLCTRL */ #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN (1 << 23) -#define DSIM_PLL_P(x) ((x) << 13) +#define DSIM_PLL_P(x, offset) ((x) << (offset)) #define DSIM_PLL_M(x) ((x) << 4) #define DSIM_PLL_S(x) ((x) << 1) @@ -263,6 +263,7 @@ struct exynos_dsi_driver_data { unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol; + unsigned int pll_p_offset; const unsigned int *reg_values; }; @@ -471,6 +472,7 @@ static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -483,6 +485,7 @@ static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -493,6 +496,7 @@ static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -504,6 +508,7 @@ static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 0, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5433_reg_values, }; @@ -515,6 +520,7 @@ static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 1, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5422_reg_values, }; @@ -628,7 +634,8 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, writel(driver_data->reg_values[PLL_TIMER], dsi->reg_base + driver_data->plltmr_reg); - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | + DSIM_PLL_M(m) | DSIM_PLL_S(s); if (driver_data->has_freqband) { static const unsigned long freq_bands[] = {