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id 1C.26.08802.1BEDDD26; Mon, 25 Jul 2022 09:07:13 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220725000713epsmtip2434fe7b72b7009e144b5219f3ec04a2e~E6c3p9AiJ0880108801epsmtip2F; Mon, 25 Jul 2022 00:07:13 +0000 (GMT) From: Chanho Park To: Krzysztof Kozlowski , Rob Herring , Vinod Koul , Kishon Vijay Abraham I Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Chanho Park , Krzysztof Kozlowski Subject: [PATCH RESEND v2] dt-bindings: phy: samsung,ufs-phy: match clock items Date: Mon, 25 Jul 2022 09:02:49 +0900 Message-Id: <20220725000249.30509-1-chanho61.park@samsung.com> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKJsWRmVeSWpSXmKPExsWy7bCmue6me3eTDP6fZrR4MG8bm8Xl/doW 84+cY7W48LSHzaLvxUNmi72vt7JbbHp8jdViwqpvLBYzzu9jsmjde4TdYuedE8wO3B6bVnWy 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6h7zz+3dJZ9gxb/58vZH9hwG58Ke7p28sP3q0g96m85X1UQUMJhVXrv9L6v8/pJNa+O+u+uv m5nLX7VjZtetnb0snHKnbvJNLKlawpjMstfr44lvKZd2cdR75bzccWvTK6fnSalmjUIBzj6T 969SeM7Jlh8fdahWYdqZqlhBZq1zVgd5Jm299WiuRzzXDJdEhR1HylfLLFJiKc5INNRiLipO BADVYeTA2AIAAA== X-CMS-MailID: 20220725000713epcas2p38d5c9d7ccdd06dd50267b72847cadc18 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220725000713epcas2p38d5c9d7ccdd06dd50267b72847cadc18 References: Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Below error is detected from dtbs_check. exynos7-ufs-phy is required symbol clocks otherwise only PLL ref clock is required. clock-names: ['ref_clk'] is too short Reported-by: Krzysztof Kozlowski Suggested-by: Krzysztof Kozlowski Suggested-by: Alim Akhtar Signed-off-by: Chanho Park Reviewed-by: Krzysztof Kozlowski --- Resend for phy maintainer - Add Krzysztof's R-B tag Changes since v1: - Move allOf: block location after required: - Remove unnecessary spaces of clock descriptions .../bindings/phy/samsung,ufs-phy.yaml | 47 +++++++++++++++---- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml index 8da99461e817..346eb7cf29a5 100644 --- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml @@ -27,18 +27,12 @@ properties: - const: phy-pma clocks: - items: - - description: PLL reference clock - - description: symbol clock for input symbol ( rx0-ch0 symbol clock) - - description: symbol clock for input symbol ( rx1-ch1 symbol clock) - - description: symbol clock for output symbol ( tx0 symbol clock) + minItems: 1 + maxItems: 4 clock-names: - items: - - const: ref_clk - - const: rx1_symbol_clk - - const: rx0_symbol_clk - - const: tx0_symbol_clk + minItems: 1 + maxItems: 4 samsung,pmu-syscon: $ref: '/schemas/types.yaml#/definitions/phandle-array' @@ -62,6 +56,39 @@ required: - clock-names - samsung,pmu-syscon +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7-ufs-phy + + then: + properties: + clocks: + items: + - description: PLL reference clock + - description: symbol clock for input symbol (rx0-ch0 symbol clock) + - description: symbol clock for input symbol (rx1-ch1 symbol clock) + - description: symbol clock for output symbol (tx0 symbol clock) + + clock-names: + items: + - const: ref_clk + - const: rx1_symbol_clk + - const: rx0_symbol_clk + - const: tx0_symbol_clk + + else: + properties: + clocks: + items: + - description: PLL reference clock + + clock-names: + items: + - const: ref_clk + additionalProperties: false examples: