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([103.51.72.28]) by smtp.gmail.com with ESMTPSA id g24-20020a170902d5d800b0015e8d4eb2e3sm4568687plh.301.2022.05.14.23.42.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 23:42:14 -0700 (PDT) From: Anand Moon To: Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J. Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui , Alim Akhtar , linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Anand Moon Subject: [PATCHv2 2/6] thermal: exynos: Reorder the gpu clock initialization for exynos5420 SoC Date: Sun, 15 May 2022 06:41:19 +0000 Message-Id: <20220515064126.1424-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515064126.1424-1-linux.amoon@gmail.com> References: <20220515064126.1424-1-linux.amoon@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Reorder the tmu_gpu clock initialization for exynos5422 SoC. Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Anand Moon --- v1: split the changes and improve the commit messages --- drivers/thermal/samsung/exynos_tmu.c | 43 ++++++++++++++-------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 75b3afadb5be..1ef90dc52c08 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -1044,42 +1044,41 @@ static int exynos_tmu_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Failed to get clock\n"); ret = PTR_ERR(data->clk); goto err_sensor; - } - - data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); - if (IS_ERR(data->clk_sec)) { - if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { - dev_err(&pdev->dev, "Failed to get triminfo clock\n"); - ret = PTR_ERR(data->clk_sec); - goto err_sensor; - } } else { - ret = clk_prepare_enable(data->clk_sec); + ret = clk_prepare_enable(data->clk); if (ret) { dev_err(&pdev->dev, "Failed to get clock\n"); goto err_sensor; } } - ret = clk_prepare_enable(data->clk); - if (ret) { - dev_err(&pdev->dev, "Failed to get clock\n"); - goto err_clk_sec; - } - switch (data->soc) { + case SOC_ARCH_EXYNOS5420_TRIMINFO: + data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); + if (IS_ERR(data->clk_sec)) { + dev_err(&pdev->dev, "Failed to get triminfo clock\n"); + ret = PTR_ERR(data->clk_sec); + goto err_clk_apbif; + } else { + ret = clk_prepare_enable(data->clk_sec); + if (ret) { + dev_err(&pdev->dev, "Failed to get clock\n"); + goto err_clk_apbif; + } + } + break; case SOC_ARCH_EXYNOS5433: case SOC_ARCH_EXYNOS7: data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); if (IS_ERR(data->sclk)) { dev_err(&pdev->dev, "Failed to get sclk\n"); ret = PTR_ERR(data->sclk); - goto err_clk; + goto err_clk_sec; } else { ret = clk_prepare_enable(data->sclk); if (ret) { dev_err(&pdev->dev, "Failed to enable sclk\n"); - goto err_clk; + goto err_clk_sec; } } break; @@ -1119,13 +1118,13 @@ static int exynos_tmu_probe(struct platform_device *pdev) err_thermal: thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); -err_sclk: - clk_disable_unprepare(data->sclk); -err_clk: - clk_disable_unprepare(data->clk); err_clk_sec: if (!IS_ERR(data->clk_sec)) clk_disable_unprepare(data->clk_sec); +err_sclk: + clk_disable_unprepare(data->sclk); +err_clk_apbif: + clk_disable_unprepare(data->clk); err_sensor: if (!IS_ERR(data->regulator)) regulator_disable(data->regulator);