From patchwork Wed Mar 30 14:50:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 555498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DB16C4167D for ; Wed, 30 Mar 2022 14:52:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347416AbiC3OyQ (ORCPT ); Wed, 30 Mar 2022 10:54:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347549AbiC3Owq (ORCPT ); Wed, 30 Mar 2022 10:52:46 -0400 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4176F4BB8D; Wed, 30 Mar 2022 07:50:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648651845; x=1680187845; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JRPEkMnKDw9JPPbw88zq0rtI6tRwyN3327TqTtQiGC4=; b=DYCUONWXk0q/GgfqEMJUyNHvE7cXVzx1/79LY79a7DQieNJJW1d5rJuR AMbxc5Q1Es9cLDMO/SXCO84Yh+WnHl5F6FaNXltSCN9nD61FqG+IYCEX2 l548szhGU4bFgJhcBPxBzRmnSpRpeFgpZUt1G+ZI1Pi5xMxtjKd5ca3mi vgrw9yEur8M0SqxpGWfGSUCQLgyGHTeqNMR8P/Y3muFTeeeBrtUIhJ9dZ mB1i8H53GtffThKCpQkM/lRkL7BnzI+FAVAzVKGTY/zNXm+j47HV+Y7Et cjEA+iFLGzLP/qPlhrunflb7YMFe7TD9E3e8/pPZk3yujc7t4sKsKZMhL g==; X-IronPort-AV: E=McAfee;i="6200,9189,10301"; a="320259364" X-IronPort-AV: E=Sophos;i="5.90,222,1643702400"; d="scan'208";a="320259364" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 07:50:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,222,1643702400"; d="scan'208";a="546889513" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga007.jf.intel.com with ESMTP; 30 Mar 2022 07:50:20 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 94D90612; Wed, 30 Mar 2022 17:50:33 +0300 (EEST) From: Andy Shevchenko To: Qianggui Song , Andy Shevchenko , Geert Uytterhoeven , Krzysztof Kozlowski , Fabien Dessenne , Linus Walleij , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-renesas-soc@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Cc: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Tomasz Figa , Sylwester Nawrocki , Alim Akhtar , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski , Philipp Zabel Subject: [PATCH v3 09/13] pinctrl: meson: Rename REG_* to MESON_REG_* Date: Wed, 30 Mar 2022 17:50:26 +0300 Message-Id: <20220330145030.1562-10-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330145030.1562-1-andriy.shevchenko@linux.intel.com> References: <20220330145030.1562-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Rename REG_* to MESON_REG_* as a prerequisite for enabling COMPILE_TEST. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/meson/pinctrl-meson.c | 24 ++++++++++++------------ drivers/pinctrl/meson/pinctrl-meson.h | 24 ++++++++++++------------ 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 49851444a6e3..5b46a0979db7 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -218,13 +218,13 @@ static int meson_pinconf_set_output(struct meson_pinctrl *pc, unsigned int pin, bool out) { - return meson_pinconf_set_gpio_bit(pc, pin, REG_DIR, !out); + return meson_pinconf_set_gpio_bit(pc, pin, MESON_REG_DIR, !out); } static int meson_pinconf_get_output(struct meson_pinctrl *pc, unsigned int pin) { - int ret = meson_pinconf_get_gpio_bit(pc, pin, REG_DIR); + int ret = meson_pinconf_get_gpio_bit(pc, pin, MESON_REG_DIR); if (ret < 0) return ret; @@ -236,13 +236,13 @@ static int meson_pinconf_set_drive(struct meson_pinctrl *pc, unsigned int pin, bool high) { - return meson_pinconf_set_gpio_bit(pc, pin, REG_OUT, high); + return meson_pinconf_set_gpio_bit(pc, pin, MESON_REG_OUT, high); } static int meson_pinconf_get_drive(struct meson_pinctrl *pc, unsigned int pin) { - return meson_pinconf_get_gpio_bit(pc, pin, REG_OUT); + return meson_pinconf_get_gpio_bit(pc, pin, MESON_REG_OUT); } static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc, @@ -269,7 +269,7 @@ static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); + meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, ®, &bit); ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); if (ret) return ret; @@ -288,7 +288,7 @@ static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin, if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); + meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, ®, &bit); if (pull_up) val = BIT(bit); @@ -296,7 +296,7 @@ static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin, if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); + meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, ®, &bit); ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); if (ret) return ret; @@ -321,7 +321,7 @@ static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc, if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); + meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, ®, &bit); if (drive_strength_ua <= 500) { ds_val = MESON_PINCONF_DRV_500UA; @@ -407,7 +407,7 @@ static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); + meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, ®, &bit); ret = regmap_read(pc->reg_pullen, reg, &val); if (ret) @@ -416,7 +416,7 @@ static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) if (!(val & BIT(bit))) { conf = PIN_CONFIG_BIAS_DISABLE; } else { - meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); + meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, ®, &bit); ret = regmap_read(pc->reg_pull, reg, &val); if (ret) @@ -447,7 +447,7 @@ static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc, if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); + meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, ®, &bit); ret = regmap_read(pc->reg_ds, reg, &val); if (ret) @@ -595,7 +595,7 @@ static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) if (ret) return ret; - meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); + meson_calc_reg_and_bit(bank, gpio, MESON_REG_IN, ®, &bit); regmap_read(pc->reg_gpio, reg, &val); return !!(val & BIT(bit)); diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index ff5372e0a475..fa042cd6a7ff 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -63,12 +63,12 @@ struct meson_reg_desc { * enum meson_reg_type - type of registers encoded in @meson_reg_desc */ enum meson_reg_type { - REG_PULLEN, - REG_PULL, - REG_DIR, - REG_OUT, - REG_IN, - REG_DS, + MESON_REG_PULLEN, + MESON_REG_PULL, + MESON_REG_DIR, + MESON_REG_OUT, + MESON_REG_IN, + MESON_REG_DS, NUM_REG, }; @@ -150,12 +150,12 @@ struct meson_pinctrl { .irq_first = fi, \ .irq_last = li, \ .regs = { \ - [REG_PULLEN] = { per, peb }, \ - [REG_PULL] = { pr, pb }, \ - [REG_DIR] = { dr, db }, \ - [REG_OUT] = { or, ob }, \ - [REG_IN] = { ir, ib }, \ - [REG_DS] = { dsr, dsb }, \ + [MESON_REG_PULLEN] = { per, peb }, \ + [MESON_REG_PULL] = { pr, pb }, \ + [MESON_REG_DIR] = { dr, db }, \ + [MESON_REG_OUT] = { or, ob }, \ + [MESON_REG_IN] = { ir, ib }, \ + [MESON_REG_DS] = { dsr, dsb }, \ }, \ }