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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id t17sm116123oor.3.2020.10.28.13.47.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2020 13:47:01 -0700 (PDT) From: Rob Herring To: Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, Andy Gross , Binghui Wang , Bjorn Andersson , Bjorn Helgaas , Fabio Estevam , Gustavo Pimentel , Jerome Brunet , Jesper Nilsson , Jingoo Han , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Martin Blumenstingl , Masahiro Yamada , Minghuan Lian , Mingkai Hu , Murali Karicheri , Neil Armstrong , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Roy Zang , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Thomas Petazzoni , Xiaowei Song , Yue Wang Subject: [PATCH 05/13] PCI: dwc: Ensure all outbound ATU windows are reset Date: Wed, 28 Oct 2020 15:46:38 -0500 Message-Id: <20201028204646.356535-6-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028204646.356535-1-robh@kernel.org> References: <20201028204646.356535-1-robh@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The Layerscape driver clears the ATU registers which may have been configured by the bootloader. Any driver could have the same issue and doing it for all drivers doesn't hurt, so let's move it into the common DWC code. Cc: Minghuan Lian Cc: Mingkai Hu Cc: Roy Zang Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Jingoo Han Cc: Gustavo Pimentel Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Rob Herring Acked-by: Jingoo Han --- drivers/pci/controller/dwc/pci-layerscape.c | 14 -------------- drivers/pci/controller/dwc/pcie-designware-host.c | 5 +++++ 2 files changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index f24f79a70d9a..53e56d54c482 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -83,14 +83,6 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) iowrite32(val, pci->dbi_base + PCIE_STRFMR1); } -static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie) -{ - int i; - - for (i = 0; i < PCIE_IATU_NUM; i++) - dw_pcie_disable_atu(pcie->pci, i, DW_PCIE_REGION_OUTBOUND); -} - static int ls1021_pcie_link_up(struct dw_pcie *pci) { u32 state; @@ -136,12 +128,6 @@ static int ls_pcie_host_init(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct ls_pcie *pcie = to_ls_pcie(pci); - /* - * Disable outbound windows configured by the bootloader to avoid - * one transaction hitting multiple outbound windows. - * dw_pcie_setup_rc() will reconfigure the outbound windows. - */ - ls_pcie_disable_outbound_atus(pcie); ls_pcie_fix_error_response(pcie); dw_pcie_dbi_ro_wr_en(pci); diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index cde45b2076ee..265a48f1a0ae 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -534,6 +534,7 @@ static struct pci_ops dw_pcie_ops = { void dw_pcie_setup_rc(struct pcie_port *pp) { + int i; u32 val, ctrl, num_ctrls; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -583,6 +584,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp) PCI_COMMAND_MASTER | PCI_COMMAND_SERR; dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + /* Ensure all outbound windows are disabled so there are multiple matches */ + for (i = 0; i < pci->num_viewport; i++) + dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND); + /* * If the platform provides its own child bus config accesses, it means * the platform uses its own address translation component rather than