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Mon, 19 Oct 2020 09:47:39 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20201019094738eusmtrp2df949d4a7d4a9a60c297b83b9298b218~-W7zXN1OJ2609626096eusmtrp2L; Mon, 19 Oct 2020 09:47:38 +0000 (GMT) X-AuditID: cbfec7f2-7efff70000001938-31-5f8d60bbb1f6 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 6B.CB.06017.AB06D8F5; Mon, 19 Oct 2020 10:47:38 +0100 (BST) Received: from AMDC2765.digital.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20201019094738eusmtip13c4a5a349e0a656bbd25ba56161d6ca5~-W7ywps621180211802eusmtip1u; Mon, 19 Oct 2020 09:47:38 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH 2/6] Documetation: dt-bindings: add the samsung, exynos-pcie binding Date: Mon, 19 Oct 2020 11:47:11 +0200 Message-Id: <20201019094715.15343-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201019094715.15343-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSbUhTYRiGec/Zdo7SidMUfbFUWBkq5AdJHdLMwuD0w+hPEMGcxzyp5dQ2 Z+mfzKXlstSQnBJ+JSrLz2XmNCVtudLchkIM0nREZToRnOZXam5H7d9938918zy8vDgqfMH3 wpNTM1hZKpMiErjyOgdXjcd64h5LQvL6fam63CSqSm/kU5a1fD7VuFiOUeYfhQLKZGrDqLHu 5wJqpNIgoNSmPoSyrU9jVLN+AqPyevUYpRv/iEYRdFNlE6B1FRMYXa1V0FpNgYB+0qEBtMHy BqHtWp9L2FXXiAQ2JTmTlQVHxrkmmX/1I+ka7zuTyhokB7R7qIALDskwuKJ7haqAKy4kGwHs W3jL58wigNX3rQLO2AF89qWYv1tZ6+rlcYMGALv/zvL2Ku0Nj1AHJSBDoWpOtV3HcXcyCq4s UQ4GJWtRmFOkBw7GjbwMP20MO3ke6Qd/FnzlOTRBnoYtdtvONl/4su2dk3EhI6Gqpt55LCTr Mdh6rxfjoGiYO7kMOO0GZwwdO/khuKWrQriCEkCrsRnjTCGAY7nqnUY4HDeuOU9FyQDY2h3M xWdh04NFxBFDcj+0zB1wxOi2fNpZhnIxAR/mCzn6KKwwtOyt7TePopymYctmKcI9UAmAU1Nq pBj4VvxfVg2ABniyCrk0kZWHprK3g+SMVK5ITQy6libVgu2vM7xpWOgCS6PxA4DEgWgfMZVW KBHymUx5lnQAQBwVuRPnRoZjhUQCk5XNytIkMkUKKx8AB3GeyJM4XvtbLCQTmQz2Jsums7Ld KYK7eOWAwJMbXUZkiln4Psooz5fdmD/iLjWX2saX+8R675jw1/78M8nGP1bboITuHLrr17M8 XfJNXUKJhtY+exT5GNpOlcdviZmYC9leswlu/rGHr3d4mGoDo9ctYbUhdYR1PsAwY3+/GmC+ dWVY5DJ38cSMtrk3zhQSIVbWZ8t0H3xEPHkSExqIyuTMPy6QyDU2AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmphkeLIzCtJLcpLzFFi42I5/e/4Xd1dCb3xBl8nmVksacqwmH/kHKvF jV9trBYrvsxkt7jwtIfN4vz5DewWl3fNYbM4O+84m8WM8/uYLN78fsFusfbIXXaL1r1H2C12 3jnB7MDrsWbeGkaPnbPusnss2FTqsWlVJ5tH35ZVjB7Hb2xn8vi8SS6APUrPpii/tCRVISO/ uMRWKdrQwkjP0NJCz8jEUs/Q2DzWyshUSd/OJiU1J7MstUjfLkEv48Lzg0wFq2Qr7jcvZGpg 3CjWxcjJISFgIvFrx16WLkYuDiGBpYwS2/evY4NIyEicnNbACmELS/y51sUGUfSJUeLU8T9g RWwChhJdb7vAbBEBJ4n3ky8ygxQxC6xhlmhs62YCSQgLBEtcPDQRbBKLgKrEs87bLCA2r4Ct xLrPb6A2yEus3nCAGcTmFLCT6Fq4DMwWAqrpWjmNZQIj3wJGhlWMIqmlxbnpucVGesWJucWl eel6yfm5mxiBMbDt2M8tOxi73gUfYhTgYFTi4X2Q3xMvxJpYVlyZe4hRgoNZSYTX6ezpOCHe lMTKqtSi/Pii0pzU4kOMpkBHTWSWEk3OB8ZnXkm8oamhuYWlobmxubGZhZI4b4fAwRghgfTE ktTs1NSC1CKYPiYOTqkGxo7dFndLyqeLvedlD1rY/HTWCfOWo+r79D2ZL233mpNonh2nsEJj 1/N5ff/CZx6Mn5/HVfsmsMTy7K2K9SFn2ORqnVf9elPXGzLpx7ZJ+2Ol5odu5z4tZXplE1/c G48fgez/2LcFHFHcvKM+7vWmBdNnR25my9RzXWx1o6k4V1T9JZvVQ6mf25VYijMSDbWYi4oT Aez6wzeXAgAA X-CMS-MailID: 20201019094739eucas1p18cd4c7e5a0197393d2e7c5c6fcc2777d X-Msg-Generator: CA X-RootMTR: 20201019094739eucas1p18cd4c7e5a0197393d2e7c5c6fcc2777d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201019094739eucas1p18cd4c7e5a0197393d2e7c5c6fcc2777d References: <20201019094715.15343-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Jaehoon Chung Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433 variant). Signed-off-by: Jaehoon Chung [mszyprow: updated the binding to latest driver changes, rewrote it in yaml, rewrote commit message] Signed-off-by: Marek Szyprowski --- .../bindings/pci/samsung,exynos-pcie.yaml | 106 ++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml new file mode 100644 index 000000000000..48fb569c238c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe Host Controller Device Tree Bindings + +maintainers: + - Jaehoon Chung + +description: |+ + Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + designware-pcie.txt. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + enum: + - samsung,exynos5433-pcie + + reg: + items: + - description: External Local Bus interface (ELBI) registers. + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: elbi + - const: bdi + - const: config + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PCIe bridge clock + - description: PCIe bus clock + + clock-names: + items: + - const: pcie + - const: pcie_bus + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + vdd10-supply: + description: + Phandle to a regulator that provides 1.0V power to the PCIe block. + + vdd18-supply: + description: + Phandle to a regulator that provides 1.8V power to the PCIe block. + +required: + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - phys + - phy-names + - vdd10-supply + +examples: + - | + #include + #include + #include + + pcie: pcie@15700000 { + compatible = "samsung,exynos5433-pcie"; + reg = <0x156b0000 0x1000>, <0x15700000 0x1000>, <0x0c000000 0x1000>; + reg-names = "elbi", "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = ; + clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; + clock-names = "pcie", "pcie_bus"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_bus &pcie_wlanen>; + num-lanes = <1>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + vdd10-supply = <&ldo6_reg>; + vdd18-supply = <&ldo7_reg>; + iterrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + };