From patchwork Fri Aug 21 03:54:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 248073 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp41ils; Thu, 20 Aug 2020 20:56:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyotrhN2Z6Q1I5k371LsS5oHshKwLzkhIrJ+zNhb13/qIw8kGyQJzbMc7w69D3XbkfwiEqq X-Received: by 2002:aa7:c0d8:: with SMTP id j24mr1013664edp.338.1597982192714; Thu, 20 Aug 2020 20:56:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1597982192; cv=none; d=google.com; s=arc-20160816; b=MID18uZJkbjmdvuy/S9uC+qBgFhbdCG694riBg2ytYqSppvOMZoiGoztbYDu/SAEaJ mE3ragHHPiUfRnx2lWhWZRRgakj3KW+csxwfVSNMwRmgRICQg44Jk+BIxeBWguR5erOP QYt/g4thx8wTa0inkWUB0n4wlIjsZ1ReDfPZmcydmnuQoKVOUprHvGayFk+kFKkWwEN5 WTaeQS7P/B7tMVh5XqpvVACXbO6xJJYB9uTaw6j6JUIdMu9Vy7+MP2xnQuCAV3RWcUmO i5jQ92fLfDFay1jKbs0+zyCKBrZROjdRkB7PYp1Mio1V373EzcYWgbB3H3QpPtvCb1q3 KqOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=qBhQHSRC5b7EjXLe1wtIsk2mRWkusWFFlluCqZMlR3s=; b=XndQDXpZf+yxxlO/epP7oZdWzbmBif07nzzB7otstQHMqavj95RaqP7M9rXVjyzAE5 0MoBfdQZEk1w5eBTP9dZGhO0xBF8T2yTJCuHXxviJNJPn8eZYt8TgIB8oIi1YzUdtl6P DlmqLXDhKcgDhaCGwsqLCSWj+howEjPvpg0AMsWwejPNmdfzu+5CqRw++rlDfFoTs52o oood/U41xsuBopHEBue+Z+10Bw8t3DwpvvFFBFlbqc2THmkh70JKexsv32meqxhkK3KS hGBxkR0HtN0r34lxvJnfarAuMdEH1w9qgfoCmNa4u1EOXyJs9um56p1zZTtHbYDtUFte 0V0A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id lv25si383713ejb.396.2020.08.20.20.56.32; Thu, 20 Aug 2020 20:56:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727831AbgHUD4c (ORCPT + 4 others); Thu, 20 Aug 2020 23:56:32 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:39267 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727082AbgHUD4a (ORCPT ); Thu, 20 Aug 2020 23:56:30 -0400 Received: by mail-io1-f68.google.com with SMTP id z17so473493ioi.6; Thu, 20 Aug 2020 20:56:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qBhQHSRC5b7EjXLe1wtIsk2mRWkusWFFlluCqZMlR3s=; b=n5DzGYJNeEG+RgU23YQHXIfx037E6/EkBEj85zJk0Z5sJtnPJspGgH6xfa3mLUybno UtXo1uWC/ZmLGcB3nuaVf/g+IDQ3vv6qFxKZDrSS48WXrYCzkB9BEvSsE61yky6ci+Gc +aILEfQrcesVCry5yikbDbCsk+3evfU6gowGDAkIiVeGjmka4FAfzkHZRgoEx4+bJtF8 JaAqVWBOkGj7Zz72xte0+Nm8s+1hP2QhItRsPsdD2dm0E3D/aQerr3CSTZQPKUe9BOKG C2aGIJfQv7TYhBR1FGtuw+z42NW2vXxOrPiR4EKq7hy+4D3UETwCFezWBeqkL2/7FHx1 xSWw== X-Gm-Message-State: AOAM531qOY/DrYHQxcB5sbRZ+2XKMjUkPkXa36Kar+QvtISgbarkxnSQ 4n4Rw/h0ty/Zs87J+p415g== X-Received: by 2002:a6b:e517:: with SMTP id y23mr896790ioc.190.1597982188440; Thu, 20 Aug 2020 20:56:28 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.249]) by smtp.googlemail.com with ESMTPSA id 79sm413923ilc.9.2020.08.20.20.56.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2020 20:56:27 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, Andy Gross , Binghui Wang , Bjorn Andersson , Dilip Kota , Fabio Estevam , Gustavo Pimentel , Jerome Brunet , Jesper Nilsson , Jingoo Han , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , Lucas Stach , Martin Blumenstingl , Masahiro Yamada , Murali Karicheri , Neil Armstrong , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang , Marc Zyngier , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 30/40] PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset Date: Thu, 20 Aug 2020 21:54:10 -0600 Message-Id: <20200821035420.380495-31-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200821035420.380495-1-robh@kernel.org> References: <20200821035420.380495-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org While the Designware controller appears to hard code the PCI_CAP_ID_EXP capability register at 0x70, there's no need to hard code this in the driver as it is discoverable. Cc: Kishon Vijay Abraham I Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Murali Karicheri Cc: Pratyush Anand Cc: linux-omap@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-dra7xx.c | 4 +--- drivers/pci/controller/dwc/pci-keystone.c | 11 +++++------ drivers/pci/controller/dwc/pcie-spear13xx.c | 4 +--- 3 files changed, 7 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index dc387724cf08..d42e0664f378 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -73,8 +73,6 @@ #define LINK_UP BIT(16) #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF -#define EXP_CAP_ID_OFFSET 0x70 - #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124 #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128 @@ -142,7 +140,7 @@ static int dra7xx_pcie_establish_link(struct dw_pcie *pci) struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); struct device *dev = pci->dev; u32 reg; - u32 exp_cap_off = EXP_CAP_ID_OFFSET; + u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); if (dw_pcie_link_up(pci)) { dev_err(dev, "link is already up\n"); diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 0fe792f6c253..39a5a72de340 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -96,8 +96,6 @@ #define LEG_EP 0x1 #define RC 0x2 -#define EXP_CAP_ID_OFFSET 0x70 - #define KS_PCIE_SYSCLOCKOUTEN BIT(0) #define AM654_PCIE_DEV_TYPE_MASK 0x3 @@ -1125,22 +1123,23 @@ static int ks_pcie_am654_set_mode(struct device *dev, static void ks_pcie_set_link_speed(struct dw_pcie *pci, int link_speed) { u32 val; + u32 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); dw_pcie_dbi_ro_wr_en(pci); - val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP); + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= link_speed; - dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP, + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); } - val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2); + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= link_speed; - dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2, + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, val); } diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c index 62846562da0b..056c94541a22 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -65,8 +65,6 @@ struct pcie_app_reg { /* CR6 */ #define MSI_CTRL_INT (1 << 26) -#define EXP_CAP_ID_OFFSET 0x70 - #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev) static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) @@ -75,7 +73,7 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) struct pcie_port *pp = &pci->pp; struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; u32 val; - u32 exp_cap_off = EXP_CAP_ID_OFFSET; + u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); if (dw_pcie_link_up(pci)) { dev_err(pci->dev, "link already up\n");