From patchwork Fri Aug 21 03:54:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 257353 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CD23C433E3 for ; Fri, 21 Aug 2020 03:56:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1E9F020714 for ; Fri, 21 Aug 2020 03:56:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597982190; bh=SZMSGeuly+5nS0AtXtxQhoq+metEQSJEONHG7JZuUEM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=0eU77AJPLetItjyqX2SvUYxCKEU739YeTkUxEiVWWJs6M3pJkrpA4ejJVc+q74cSD 6NPZA20Vv048mn1h0Nvb3PpULrHkMu8tZPnRym4y8yFW/5b3y91PsmvCLQ16mkTswv aH5VI1ACcgOIsispth9NGIdI7n7CUFo6FTzTIWFs= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727909AbgHUD42 (ORCPT ); Thu, 20 Aug 2020 23:56:28 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:40615 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728040AbgHUD40 (ORCPT ); Thu, 20 Aug 2020 23:56:26 -0400 Received: by mail-io1-f65.google.com with SMTP id b17so473393ion.7; Thu, 20 Aug 2020 20:56:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=edvGUGpaPjRq5umLUm+6u58eZpeK1XpSMHPWcWJ22Uc=; b=UeCersc32yRemzL4IlseLVNQEUMUzTbmw0gdfgK1I0WF2BvhtsEiS9VhBGjCGgYNFB 0BWZJugI7xR8P2mnS5jbJEIs0NdfiGD3bJUFhNuwyCbqu3tR/jRx2Cl+mQ8KunEj3IR4 8fQ6T17s2SDLYlpYz98NURpffpP3OBxz+nwed8UDSLjnzT854e9gLUgZZj1MPs5pxqui jsQSEcCr5KYNd6tbpXzCWwK84JOz7qvDq7RvtRIBpcPmQ8qWZR/4jUC62YtFFawuOqBf nuIB0YL6S1Z8dQ0U/P2VW1kAg7yFcV0FvmrDIeKhZe3IfHlg7Nd6ST3zU2v9YPK01gO6 MVtA== X-Gm-Message-State: AOAM531UEHUDlnJs0Dr8LixWvGYEFeL2kkjU9wwTeTdryRwESSeLVt/8 +71RMHbdKD3fupPIoAX/SBhLtizVag== X-Google-Smtp-Source: ABdhPJzMKcXOoA67DdtZomKXJ3hcCjg+p+4UND5Vd7stRJubIRYKDJim6SwRyBPjPn5FZKEVR20Ruw== X-Received: by 2002:a6b:c94e:: with SMTP id z75mr898531iof.196.1597982185446; Thu, 20 Aug 2020 20:56:25 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.249]) by smtp.googlemail.com with ESMTPSA id 79sm413923ilc.9.2020.08.20.20.56.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2020 20:56:24 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, Andy Gross , Binghui Wang , Bjorn Andersson , Dilip Kota , Fabio Estevam , Gustavo Pimentel , Jerome Brunet , Jesper Nilsson , Jingoo Han , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , Lucas Stach , Martin Blumenstingl , Masahiro Yamada , Murali Karicheri , Neil Armstrong , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang , Marc Zyngier , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 29/40] PCI: dwc/qcom: Use common PCI register definitions Date: Thu, 20 Aug 2020 21:54:09 -0600 Message-Id: <20200821035420.380495-30-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200821035420.380495-1-robh@kernel.org> References: <20200821035420.380495-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The QCom driver has its own defines for common PCI config space registers. It also hard codes the capability register offsets which are discoverable. Convert it to use the standard register definitions. Cc: Stanimir Varbanov Cc: Andy Gross Cc: Bjorn Andersson Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index fe7fc2ccd76d..d8d1fb7e0b8f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -67,10 +67,6 @@ #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c #define CFG_BRIDGE_SB_INIT BIT(0) -#define PCIE20_CAP 0x70 -#define PCIE20_DEVICE_CONTROL2_STATUS2 (PCIE20_CAP + PCI_EXP_DEVCTL2) -#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + PCI_EXP_LNKCAP) -#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14) #define PCIE_CAP_LINK1_VAL 0x2FD7F #define PCIE20_PARF_Q2A_FLUSH 0x1AC @@ -1017,6 +1013,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int i, ret; u32 val; @@ -1092,14 +1089,14 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); - writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1); + writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); - val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); val &= ~PCI_EXP_LNKCAP_ASPMS; - writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); - writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + - PCIE20_DEVICE_CONTROL2_STATUS2); + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + + PCI_EXP_DEVCTL2); return 0; @@ -1252,7 +1249,8 @@ static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) static int qcom_pcie_link_up(struct dw_pcie *pci) { - u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA); + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); return !!(val & PCI_EXP_LNKSTA_DLLLA); }