From patchwork Fri Aug 21 03:53:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 257363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE116C433EB for ; Fri, 21 Aug 2020 03:55:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8F2CC22B47 for ; Fri, 21 Aug 2020 03:55:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597982115; bh=1ioz8IbTxWkGCeDDXsQVXucSC1+tAGq97rs8v8uUXgU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=l2ZQieM0Us3v+MPRwS1H557u3PJR04eg4eAhYQxdKLewLnotoq3O9tuKVYKwD2HiE q8poy3XPp7YYmiaByj9u3bth8tUckTH9DuQ0Md8Wk1VqPzNiSMU2x18d5nm7+Dk43n 4I90DlEYIC+3Fz2nKVkHkLptcyrsjD2pmldX8Ns8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727914AbgHUDzO (ORCPT ); Thu, 20 Aug 2020 23:55:14 -0400 Received: from mail-io1-f66.google.com ([209.85.166.66]:40519 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727900AbgHUDzK (ORCPT ); Thu, 20 Aug 2020 23:55:10 -0400 Received: by mail-io1-f66.google.com with SMTP id b17so471477ion.7; Thu, 20 Aug 2020 20:55:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nFg1YpOXTjGvAAjYWr6Bj6FfzEbwYJGtjSsSCN/Mie0=; b=K4BrF9gWGQMoXEk/8uQ5gRsEVMScPBp/PSlrM7DqpJtl4g2GIgp3BH/p2rHEJK/+Nm Xil1fH+/kkJoRwhnlZbXZSeiSaQqogZKGYkJwQyBT4I1KcYKe8gQOdchkH7wW4cSAW85 OxECeJrPVa5ZBEdaqHfFce93FH2bnSEPBYfPf4dWQNDiy4QBahOLp60pGkIXQ1HHhLHl TA3Nqf26f947eyV+zRlFXKvQvqcvEyXW8y5FOzu7dT4SqjlveS+Gxt15HuW9KVP/cwFK GRSE3mWMTI9K5Y5IeBAnw79nMl8soIbiks/V8UTQmGHDHpmtng95a6rZVFnbG6Xqo0x3 X/jA== X-Gm-Message-State: AOAM532A3XORi1U/nkBUOc5RU/O899pVfIwar/e6PQrLz57z8UwXygXP 5815+dPygaIqHTCfhXVYeA== X-Google-Smtp-Source: ABdhPJxYgLoP8TuODrHoVFznYdMs1PDoYAX/0YMmlaFkI6tCOH/kTSu793FCitBMJXoZOfNcnv5Smg== X-Received: by 2002:a6b:dc0a:: with SMTP id s10mr898987ioc.18.1597982109347; Thu, 20 Aug 2020 20:55:09 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.249]) by smtp.googlemail.com with ESMTPSA id 79sm413923ilc.9.2020.08.20.20.55.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2020 20:55:08 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, Andy Gross , Binghui Wang , Bjorn Andersson , Dilip Kota , Fabio Estevam , Gustavo Pimentel , Jerome Brunet , Jesper Nilsson , Jingoo Han , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , Lucas Stach , Martin Blumenstingl , Masahiro Yamada , Murali Karicheri , Neil Armstrong , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang , Marc Zyngier , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 09/40] PCI: dwc: kirin: Use pci_ops for root config space accessors Date: Thu, 20 Aug 2020 21:53:49 -0600 Message-Id: <20200821035420.380495-10-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200821035420.380495-1-robh@kernel.org> References: <20200821035420.380495-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the HiSilicon Kirin driver to use the standard pci_ops for root bus config accesses. Cc: Xiaowei Song Cc: Binghui Wang Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-kirin.c | 39 +++++++++++++------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index e496f51e0152..8a01ab0a4a65 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -330,34 +330,37 @@ static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR); } -static int kirin_pcie_rd_own_conf(struct pcie_port *pp, +static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true); - ret = dw_pcie_read(pci->dbi_base + where, size, val); - kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false); + if (PCI_SLOT(devfn)) { + *val = ~0; + return PCIBIOS_DEVICE_NOT_FOUND; + } - return ret; + *val = dw_pcie_read_dbi(pci, where, size); + return PCIBIOS_SUCCESSFUL; } -static int kirin_pcie_wr_own_conf(struct pcie_port *pp, +static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true); - ret = dw_pcie_write(pci->dbi_base + where, size, val); - kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false); + if (PCI_SLOT(devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; - return ret; + dw_pcie_write_dbi(pci, where, size, val); + return PCIBIOS_SUCCESSFUL; } +static struct pci_ops kirin_pci_ops = { + .read = kirin_pcie_rd_own_conf, + .write = kirin_pcie_wr_own_conf, +}; + static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size) { @@ -423,6 +426,8 @@ static int kirin_pcie_establish_link(struct pcie_port *pp) static int kirin_pcie_host_init(struct pcie_port *pp) { + pp->bridge->ops = &kirin_pci_ops; + kirin_pcie_establish_link(pp); if (IS_ENABLED(CONFIG_PCI_MSI)) @@ -438,8 +443,6 @@ static const struct dw_pcie_ops kirin_dw_pcie_ops = { }; static const struct dw_pcie_host_ops kirin_pcie_host_ops = { - .rd_own_conf = kirin_pcie_rd_own_conf, - .wr_own_conf = kirin_pcie_wr_own_conf, .host_init = kirin_pcie_host_init, };