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[198.145.29.99]) by mx.google.com with ESMTPS id d20si4127992pgl.224.2020.08.06.11.24.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Aug 2020 11:24:33 -0700 (PDT) Received-SPF: pass (google.com: domain of krzk@kernel.org designates 198.145.29.99 as permitted sender) client-ip=198.145.29.99; Received: by mail.kernel.org (Postfix) id 02FE322EBE; Thu, 6 Aug 2020 18:24:34 +0000 (UTC) Received: from localhost.localdomain (unknown [194.230.155.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5D68A230FF; Thu, 6 Aug 2020 18:24:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1596738273; bh=zSPJaWHqH2p/CnzlIYBwfeQwSQSWPlKg7XPNzrWLNhA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S5KbQ5A9Y1pof988/YmoJ7Aa3Z9HTb54MDsEFrSUXTpzc8LRFH74k+14NcynvJz4r BUrQZBTHPraTFJJmjSlc1Ft3yqBz/GxSSihYvWiOsSKQStmqnmtun1SbwMXH6YATtp +dU3HKOOTlyG8degP9b5d7+7XoeTj1PK87Xl82lw= From: Krzysztof Kozlowski To: linux-kernel@vger.kernel.org Cc: Arnd Bergmann , Krzysztof Kozlowski , Kukjin Kim , "Rafael J. Wysocki" , Viresh Kumar , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 36/41] cpufreq: s3c2412: use global s3c2412_cpufreq_setrefresh Date: Thu, 6 Aug 2020 20:20:53 +0200 Message-Id: <20200806182059.2431-36-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200806181932.2253-1-krzk@kernel.org> References: <20200806181932.2253-1-krzk@kernel.org> X-TUID: XXZn3wgYpF5u Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Arnd Bergmann There are two identical copies of the s3c2412_cpufreq_setrefresh function: a static one in the cpufreq driver and a global version in iotiming-s3c2412.c. As the function requires the use of a hardcoded register address from a header that we want to not be visible to drivers, just move the existing global function and add a declaration in one of the cpufreq header files. Signed-off-by: Arnd Bergmann Signed-off-by: Krzysztof Kozlowski --- drivers/cpufreq/s3c2412-cpufreq.c | 23 -------------------- include/linux/soc/samsung/s3c-cpufreq-core.h | 1 + 2 files changed, 1 insertion(+), 23 deletions(-) -- 2.17.1 diff --git a/drivers/cpufreq/s3c2412-cpufreq.c b/drivers/cpufreq/s3c2412-cpufreq.c index 38dc9e6db633..a77c63e92e1a 100644 --- a/drivers/cpufreq/s3c2412-cpufreq.c +++ b/drivers/cpufreq/s3c2412-cpufreq.c @@ -25,8 +25,6 @@ #include #include -#include - #include #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) @@ -156,27 +154,6 @@ static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); } -static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) -{ - struct s3c_cpufreq_board *board = cfg->board; - unsigned long refresh; - - s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__, - board->refresh, cfg->freq.hclk); - - /* Reduce both the refresh time (in ns) and the frequency (in MHz) - * by 10 each to ensure that we do not overflow 32 bit numbers. This - * should work for HCLK up to 133MHz and refresh period up to 30usec. - */ - - refresh = (board->refresh / 10); - refresh *= (cfg->freq.hclk / 100); - refresh /= (1 * 1000 * 1000); /* 10^6 */ - - s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh); - __raw_writel(refresh, S3C2412_REFRESH); -} - /* set the default cpu frequency information, based on an 200MHz part * as we have no other way of detecting the speed rating in software. */ diff --git a/include/linux/soc/samsung/s3c-cpufreq-core.h b/include/linux/soc/samsung/s3c-cpufreq-core.h index c578b07ccd5d..e0c7217a0f53 100644 --- a/include/linux/soc/samsung/s3c-cpufreq-core.h +++ b/include/linux/soc/samsung/s3c-cpufreq-core.h @@ -248,6 +248,7 @@ extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, struct s3c_iotimings *iot); +extern void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg); #else #define s3c2412_iotiming_debugfs NULL #define s3c2412_iotiming_calc NULL