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Fri, 17 Apr 2020 18:10:10 +0000 (GMT) From: Alim Akhtar To: robh@kernel.org Cc: devicetree@vger.kernel.org, linux-scsi@vger.kernel.org, krzk@kernel.org, avri.altman@wdc.com, martin.petersen@oracle.com, kwmad.kim@samsung.com, stanley.chu@mediatek.com, cang@codeaurora.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alim Akhtar Subject: [PATCH v6 03/10] scsi: ufs: add quirk to enable host controller without hce Date: Fri, 17 Apr 2020 23:29:37 +0530 Message-Id: <20200417175944.47189-4-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200417175944.47189-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIKsWRmVeSWpSXmKPExsWy7bCmhi7rx5lxBhOnS1g8mLeNzeLlz6ts Fp/WL2O1mH/kHKvF+fMb2C1ubjnKYrHp8TVWi8u75rBZzDi/j8mi+/oONovlx/8xWfzfs4Pd YunWm4wOvB6X+3qZPDat6mTz2Lyk3qPl5H4Wj49Pb7F49G1ZxejxeZOcR/uBbqYAjigum5TU nMyy1CJ9uwSujHP/rrIVXJGtWNiygaWB8Yd4FyMnh4SAicTP/bPZuxi5OIQEdjNKHJv5F8r5 xCgx9Ws7G4TzjVFi4bWLrDAt7z/PZYJI7GWU6L56nxnCaWGSeLpoFQtIFZuAtsTd6VuYQGwR AWGJI9/aGEFsZoEbTBIPVrqA2MICYRK/p2xlB7FZBFQlDs86BGbzCthINPR9ZYLYJi+xesMB ZhCbU8BWoq1lKdhmCYHbbBJr+s+xQBS5SCxpeswOYQtLvDq+BcqWknjZ3wZkcwDZ2RI9u4wh wjUSS+cdg2q1lzhwZQ4LSAmzgKbE+l36EGfySfT+fsIE0ckr0dEmBFGtKtH87ipUp7TExO5u aJh4SOyYAhIHBcMERontu66zT2CUnYUwdQEj4ypGydSC4tz01GLTAqO81HK94sTc4tK8dL3k /NxNjOCEouW1g3HZOZ9DjAIcjEo8vB19M+OEWBPLiitzDzFKcDArifAedAMK8aYkVlalFuXH F5XmpBYfYpTmYFES553EejVGSCA9sSQ1OzW1ILUIJsvEwSnVwLhH0ENLfF5S7LplGtt2rPl7 ks9m4t2rU8LiPGpVFebd2CoobHT7z9IjgiuKbSylbX2+GT2pXOKS/rN7lpnEgcmKzQvzvXIV GXweMGfpy8cHfOJNunR7Mbd+4Oxe411zdzF+MK+Ld9/m9O3//mcv+opLmmUEbK5tv3wkSdTi Rs75/FZH25T9O5RYijMSDbWYi4oTATfuvXskAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrPLMWRmVeSWpSXmKPExsWy7bCSnC7Lx5lxBj8fslk8mLeNzeLlz6ts Fp/WL2O1mH/kHKvF+fMb2C1ubjnKYrHp8TVWi8u75rBZzDi/j8mi+/oONovlx/8xWfzfs4Pd YunWm4wOvB6X+3qZPDat6mTz2Lyk3qPl5H4Wj49Pb7F49G1ZxejxeZOcR/uBbqYAjigum5TU nMyy1CJ9uwSujHP/rrIVXJGtWNiygaWB8Yd4FyMnh4SAicT7z3OZuhi5OIQEdjNKLP7UwwSR kJa4vnECO4QtLLHy33N2iKImJonH7ZuZQRJsAtoSd6dvAWsQASo68q2NEcRmFnjGJHHqYSmI LSwQInHgZScLiM0ioCpxeNYhsKG8AjYSDX1foZbJS6zecABsJqeArURby1KgOAfQMhuJDU9i JjDyLWBkWMUomVpQnJueW2xYYJiXWq5XnJhbXJqXrpecn7uJERzMWpo7GC8viT/EKMDBqMTD a9AzM06INbGsuDL3EKMEB7OSCO9BN6AQb0piZVVqUX58UWlOavEhRmkOFiVx3qd5xyKFBNIT S1KzU1MLUotgskwcnFINjGZtDS/jajb2l+p3fvUV1/cTc5e22XL3bUWm0z57mae95UyeVZf2 CDN8iVo5o4jdxbIu5FeWzMmrB2ZxL/GueK20+gLP37v7tL5c+qZo6T0l6nT24Ygc55x+i3WH 5Auqzvzs3v3G9ehSTfGlgRXbUtssqpO74ivPPplelvaSb/6xuap1XR83KbEUZyQaajEXFScC ADNExlNiAgAA X-CMS-MailID: 20200417181012epcas5p2004ac8f0d793abd4d58c096ff490da68 X-Msg-Generator: CA CMS-TYPE: 105P X-CMS-RootMailID: 20200417181012epcas5p2004ac8f0d793abd4d58c096ff490da68 References: <20200417175944.47189-1-alim.akhtar@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Some host controllers don't support host controller enable via HCE. Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar --- drivers/scsi/ufs/ufshcd.c | 76 +++++++++++++++++++++++++++++++++++++-- drivers/scsi/ufs/ufshcd.h | 6 ++++ 2 files changed, 80 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 0e9704da58bd..ee30ed6cc805 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -3534,6 +3534,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba) "dme-link-startup: error code %d\n", ret); return ret; } +/** + * ufshcd_dme_reset - UIC command for DME_RESET + * @hba: per adapter instance + * + * DME_RESET command is issued in order to reset UniPro stack. + * This function now deal with cold reset. + * + * Returns 0 on success, non-zero value on failure + */ +static int ufshcd_dme_reset(struct ufs_hba *hba) +{ + struct uic_command uic_cmd = {0}; + int ret; + + uic_cmd.command = UIC_CMD_DME_RESET; + + ret = ufshcd_send_uic_cmd(hba, &uic_cmd); + if (ret) + dev_err(hba->dev, + "dme-reset: error code %d\n", ret); + + return ret; +} + +/** + * ufshcd_dme_enable - UIC command for DME_ENABLE + * @hba: per adapter instance + * + * DME_ENABLE command is issued in order to enable UniPro stack. + * + * Returns 0 on success, non-zero value on failure + */ +static int ufshcd_dme_enable(struct ufs_hba *hba) +{ + struct uic_command uic_cmd = {0}; + int ret; + + uic_cmd.command = UIC_CMD_DME_ENABLE; + + ret = ufshcd_send_uic_cmd(hba, &uic_cmd); + if (ret) + dev_err(hba->dev, + "dme-reset: error code %d\n", ret); + + return ret; +} static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) { @@ -4251,7 +4297,7 @@ static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep) } /** - * ufshcd_hba_enable - initialize the controller + * ufshcd_hba_execute_hce - initialize the controller * @hba: per adapter instance * * The controller resets itself and controller firmware initialization @@ -4260,7 +4306,7 @@ static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep) * * Returns 0 on success, non-zero value on failure */ -int ufshcd_hba_enable(struct ufs_hba *hba) +static int ufshcd_hba_execute_hce(struct ufs_hba *hba) { int retry; @@ -4308,6 +4354,32 @@ int ufshcd_hba_enable(struct ufs_hba *hba) return 0; } + +int ufshcd_hba_enable(struct ufs_hba *hba) +{ + int ret; + + if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { + ufshcd_set_link_off(hba); + ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); + + /* enable UIC related interrupts */ + ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); + ret = ufshcd_dme_reset(hba); + if (!ret) { + ret = ufshcd_dme_enable(hba); + if (!ret) + ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); + if (ret) + dev_err(hba->dev, + "Host controller enable failed with non-hce\n"); + } + } else { + ret = ufshcd_hba_execute_hce(hba); + } + + return ret; +} EXPORT_SYMBOL_GPL(ufshcd_hba_enable); static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index 53096642f9a8..f8d08cb9caf7 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -529,6 +529,12 @@ enum ufshcd_quirks { * that the interrupt aggregation timer and counter are reset by s/w. */ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, + + /* + * This quirks needs to be enabled if host controller cannot be + * enabled via HCE register. + */ + UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, }; enum ufshcd_caps {