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Wed, 12 Sep 2018 14:16:57 +0100 (BST) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20180912131657eucas1p2eecc0e4a01ed9ddbf4417c17eba0fee0~TqXTScDcM1446814468eucas1p2O; Wed, 12 Sep 2018 13:16:57 +0000 (GMT) X-AuditID: cbfec7f5-367ff700000012c6-16-5b9911c9af94 Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id D0.19.04284.9C1199B5; Wed, 12 Sep 2018 14:16:57 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PEY00CLF285R220@eusync1.samsung.com>; Wed, 12 Sep 2018 14:16:57 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH] clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend Date: Wed, 12 Sep 2018 15:16:41 +0200 Message-id: <20180912131641.21688-1-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEIsWRmVeSWpSXmKPExsWy7djPc7onBWdGG7z+pGyxccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3aL96UtmB3aPTas62Tz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoEr4/3t6+wFzzkqlm5+ytrAuJq9i5GTQ0LAROJiazNzFyMXh5DACkaJq8t2QDmfGSWW T34O5HCAVb3fLQkRX8YosWPuExYIp4FJYsrBx2Cj2AQMJbredrGB2CICDhKfP71mBCliFnjM KLH15FdmkISwQKjEsVmHmUBsFgFViQtX29hANvAK2EqcbwyAOEleYvWGA2BXSAg8ZJW4//wv G8QVLhKr+xwhaoQlXh3fAvWCjERnx0EmiPpmRon2GbPYIZweoMVzdrBBVFlLHD5+kRXEZhbg k5i0bTrUa7wSHW1CECUeEn271oPdJiQQK/Hk1TnGCYwSCxgZVjGKp5YW56anFhvnpZbrFSfm Fpfmpesl5+duYgTG1Ol/x7/uYNz3J+kQowAHoxIP74p906OFWBPLiitzDzFKcDArifC+Zp8Z LcSbklhZlVqUH19UmpNafIhRmoNFSZyXTystWkggPbEkNTs1tSC1CCbLxMEp1cC4jNf/mmdK ba8bt8MlixuLLB5EP+c/ltsXnd4u7y1c8bH2LPf0sPCynSxprUUzpr6UjMhe0nGqtuW66aY6 hf2yiX2LXNaoTD7z/o8J39OFvTNniwX01ty3Kd3xzTHqM5eu9oVz6W+OLzo2LVMnMONO9K4T YUe0520tnrttf7O7WlC/ZknptO9KLMUZiYZazEXFiQDGsDdupQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCJMWRmVeSWpSXmKPExsVy+t/xy7onBWdGG+y/zGyxccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3aL96UtmB3aPTas62Tz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoEr4/3t6+wFzzkqlm5+ytrAuJq9i5GDQ0LAROL9bskuRi4OIYEljBIPJjxmhnCamCTe Nk4FKuLkYBMwlOh628UGYosIOEh8/vSaEaSIWeAxo8S5xRtYQRLCAqESx2YdZgKxWQRUJS5c bWMD2cArYCtxvjEAJCwhIC+xesMB5gmMXAsYGVYxiqSWFuem5xYb6hUn5haX5qXrJefnbmIE +n3bsZ+bdzBe2hh8iFGAg1GJh3fFvunRQqyJZcWVuYcYJTiYlUR4X7PPjBbiTUmsrEotyo8v Ks1JLT7EKM3BoiTOe96gMkpIID2xJDU7NbUgtQgmy8TBKdXAyPT1+9cF32P/FUQUGaq/X7DR /Oz85sJ1oYvDTkt/kH2yzbns+4alr5YsCVm1OG/u2dKMrTUMc/tjg6aEHdtTdP/kkfg3iUcC NjvPybP6/Vr+IIeYd3WQccdsL8sZFnofe2IPKAt+ichf4r2WNef580tKnVkdGQsZM+7EsH45 ItahdkVzY3+biRJLcUaioRZzUXEiAP6K0ID3AQAA X-CMS-MailID: 20180912131657eucas1p2eecc0e4a01ed9ddbf4417c17eba0fee0 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180912131657eucas1p2eecc0e4a01ed9ddbf4417c17eba0fee0 References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org All sclk_uart clocks in TOP CMU have to be kept enabled for suspend/resume cycle, otherwise TM2(e) boards hangs before entering the suspend mode. Signed-off-by: Marek Szyprowski --- This change was missing in the initial patch, because 'no_console_suspend' kernel option did almost the same. --- drivers/clk/samsung/clk-exynos5433.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 13384f4911c7..84eac0ce5682 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -180,6 +180,8 @@ static const unsigned long top_clk_regs[] __initconst = { static const struct samsung_clk_reg_dump top_suspend_regs[] = { /* force all aclk clocks enabled */ { ENABLE_ACLK_TOP, 0x67ecffed }, + /* force all sclk_uart clocks enabled */ + { ENABLE_SCLK_TOP_PERIC, 0x38 }, /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ { ISP_PLL_CON0, 0x85cc0502 }, /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */