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Thu, 6 Sep 2018 15:55:58 +0000 (GMT) X-AuditID: cbfec7f5-367ff700000012c6-9f-5b914e0e83b9 Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id F9.DC.04128.E0E419B5; Thu, 6 Sep 2018 16:55:58 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PEN009IJ5L4PE10@eusync3.samsung.com>; Thu, 06 Sep 2018 16:55:57 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v2 09/10] clk: samsung: exynos4: Use generic helper for handling suspend/resume Date: Thu, 06 Sep 2018 17:55:31 +0200 Message-id: <20180906155532.4085-10-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-reply-to: <20180906155532.4085-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIIsWRmVeSWpSXmKPExsWy7djPc7p8fhOjDc5NlbPYOGM9q8X1L89Z Lc6f38Bu8bHnHqvFjPP7mCzWHrnLbtH+9CWzA7vHplWdbB59W1YxenzeJBfAHMVlk5Kak1mW WqRvl8CVMe/pBLaCDUYVN1tyGxibtLoYOTkkBEwkvh0/xdrFyMUhJLCCUWJS12k2COczo0TD pLmsMFV3nlxkhEgsY5R48nMRVEsDk8T81asZQarYBAwlut52sYHYIgIOEp8/vQbrYBZ4zCix 9eRXZpCEsECixOPl78HGsgioSrx5cZMdxOYVsJX4evA8O8Q6eYnVGw6A1XMCxWfM7QTbJiHw kVXiws2DUEUuEguff4C6T1ji1fEtUHEZicuTu1kgGpoZJdpnzGKHcHqAzpizgw2iylri8PGL YN3MAnwSk7ZNB1rHARTnlehoE4Io8ZDYuvMLE8SfExglljT9Z57AKLmAkWEVo3hqaXFuemqx cV5quV5xYm5xaV66XnJ+7iZGYMSd/nf86w7GfX+SDjEKcDAq8fA+MJoYLcSaWFZcmXuIUYKD WUmE1716QrQQb0piZVVqUX58UWlOavEhRmkOFiVxXj6ttGghgfTEktTs1NSC1CKYLBMHp1QD 4/aymrKTM7gY32jyLd+6Y/KBBcJzPv2pmSKxYsGEsjU1q3ZtvVmavGLbbYX1sy1P2MeuihOb 5HxZqdWIQTOe09Rt3s5DUc8nObgcWKkzYbVbs06A62SnF63zeNSYbwuUaf+f9uMW18GuVepX LbndqmJVZOf37vf6dT5oRp/VzJt6q56wPbhbUKLEUpyRaKjFXFScCABAUfBktAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLJMWRmVeSWpSXmKPExsVy+t/xq7p8fhOjDVa9Y7TYOGM9q8X1L89Z Lc6f38Bu8bHnHqvFjPP7mCzWHrnLbtH+9CWzA7vHplWdbB59W1YxenzeJBfAHMVlk5Kak1mW WqRvl8CVMe/pBLaCDUYVN1tyGxibtLoYOTkkBEwk7jy5yNjFyMUhJLCEUeLR9CtQThOTRMeG RWwgVWwChhJdb7vAbBEBB4nPn16DFTELPGaUOLd4AytIQlggUeLx8vdgNouAqsSbFzfZQWxe AVuJrwfPs0Osk5dYveEAM4jNCRSfMbcTrF5IwEZiVeMU1gmMPAsYGVYxiqSWFuem5xYb6RUn 5haX5qXrJefnbmIEBsq2Yz+37GDsehd8iFGAg1GJh9fCdGK0EGtiWXFl7iFGCQ5mJRFe9+oJ 0UK8KYmVValF+fFFpTmpxYcYpTlYlMR5zxtURgkJpCeWpGanphakFsFkmTg4pRoYc9ZcvrPo xKV/smlL9PoZeGZNrP9cdGhnv8q1sEtJiWIBrXZ31xh6+P/M55spfaD7V8yyC9xf814zP2CR /PatT3Fu58PZDcnTi12kzt4t8rG5GRu3N9r1nOlDGfPer8Eqy2x3Hmh8q7dx4+2QQtG3W6Tv C32d+myxwFSTyq4HP7XO682fL3ngpBJLcUaioRZzUXEiAE7/evAQAgAA X-CMS-MailID: 20180906155558eucas1p2778fb4476678214f4509f46a5b92dd5d X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180906155558eucas1p2778fb4476678214f4509f46a5b92dd5d References: <20180906155532.4085-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Replace common suspend/resume handling code by generic helper. Handling of PLLs is a bit different in generic code, as they are handled in the same way as other clock registers. Such approach was already used on later Exynos SoCs and worked fine. Tests have shown that it works also on Exynos4 SoCs and significantly simplifies the code. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos4.c | 145 +++--------------------------- 1 file changed, 14 insertions(+), 131 deletions(-) -- 2.17.1 diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 0421960eb963..d7cfdb0732c8 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "clk.h" #include "clk-cpu.h" @@ -157,14 +156,6 @@ enum exynos4_plls { static void __iomem *reg_base; static enum exynos4_soc exynos4_soc; -/* - * Support for CMU save/restore across system suspends - */ -#ifdef CONFIG_PM_SLEEP -static struct samsung_clk_reg_dump *exynos4_save_common; -static struct samsung_clk_reg_dump *exynos4_save_soc; -static struct samsung_clk_reg_dump *exynos4_save_pll; - /* * list of controller registers to be saved and restored during a * suspend/resume cycle. @@ -192,7 +183,7 @@ static const unsigned long exynos4x12_clk_save[] __initconst = { E4X12_PWR_CTRL2, }; -static const unsigned long exynos4_clk_pll_regs[] __initconst = { +static const unsigned long exynos4_clk_regs[] __initconst = { EPLL_LOCK, VPLL_LOCK, EPLL_CON0, @@ -201,9 +192,6 @@ static const unsigned long exynos4_clk_pll_regs[] __initconst = { VPLL_CON0, VPLL_CON1, VPLL_CON2, -}; - -static const unsigned long exynos4_clk_regs[] __initconst = { SRC_LEFTBUS, DIV_LEFTBUS, GATE_IP_LEFTBUS, @@ -276,6 +264,8 @@ static const unsigned long exynos4_clk_regs[] __initconst = { }; static const struct samsung_clk_reg_dump src_mask_suspend[] = { + { .offset = VPLL_CON0, .value = 0x80600302, }, + { .offset = EPLL_CON0, .value = 0x806F0302, }, { .offset = SRC_MASK_TOP, .value = 0x00000001, }, { .offset = SRC_MASK_CAM, .value = 0x11111111, }, { .offset = SRC_MASK_TV, .value = 0x00000111, }, @@ -291,123 +281,6 @@ static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, }, }; -#define PLL_ENABLED (1 << 31) -#define PLL_LOCKED (1 << 29) - -static void exynos4_clk_enable_pll(u32 reg) -{ - u32 pll_con = readl(reg_base + reg); - pll_con |= PLL_ENABLED; - writel(pll_con, reg_base + reg); - - while (!(pll_con & PLL_LOCKED)) { - cpu_relax(); - pll_con = readl(reg_base + reg); - } -} - -static void exynos4_clk_wait_for_pll(u32 reg) -{ - u32 pll_con; - - pll_con = readl(reg_base + reg); - if (!(pll_con & PLL_ENABLED)) - return; - - while (!(pll_con & PLL_LOCKED)) { - cpu_relax(); - pll_con = readl(reg_base + reg); - } -} - -static int exynos4_clk_suspend(void) -{ - samsung_clk_save(reg_base, exynos4_save_common, - ARRAY_SIZE(exynos4_clk_regs)); - samsung_clk_save(reg_base, exynos4_save_pll, - ARRAY_SIZE(exynos4_clk_pll_regs)); - - exynos4_clk_enable_pll(EPLL_CON0); - exynos4_clk_enable_pll(VPLL_CON0); - - if (exynos4_soc == EXYNOS4210) { - samsung_clk_save(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4210_clk_save)); - samsung_clk_restore(reg_base, src_mask_suspend_e4210, - ARRAY_SIZE(src_mask_suspend_e4210)); - } else { - samsung_clk_save(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4x12_clk_save)); - } - - samsung_clk_restore(reg_base, src_mask_suspend, - ARRAY_SIZE(src_mask_suspend)); - - return 0; -} - -static void exynos4_clk_resume(void) -{ - samsung_clk_restore(reg_base, exynos4_save_pll, - ARRAY_SIZE(exynos4_clk_pll_regs)); - - exynos4_clk_wait_for_pll(EPLL_CON0); - exynos4_clk_wait_for_pll(VPLL_CON0); - - samsung_clk_restore(reg_base, exynos4_save_common, - ARRAY_SIZE(exynos4_clk_regs)); - - if (exynos4_soc == EXYNOS4210) - samsung_clk_restore(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4210_clk_save)); - else - samsung_clk_restore(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4x12_clk_save)); -} - -static struct syscore_ops exynos4_clk_syscore_ops = { - .suspend = exynos4_clk_suspend, - .resume = exynos4_clk_resume, -}; - -static void __init exynos4_clk_sleep_init(void) -{ - exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs, - ARRAY_SIZE(exynos4_clk_regs)); - if (!exynos4_save_common) - goto err_warn; - - if (exynos4_soc == EXYNOS4210) - exynos4_save_soc = samsung_clk_alloc_reg_dump( - exynos4210_clk_save, - ARRAY_SIZE(exynos4210_clk_save)); - else - exynos4_save_soc = samsung_clk_alloc_reg_dump( - exynos4x12_clk_save, - ARRAY_SIZE(exynos4x12_clk_save)); - if (!exynos4_save_soc) - goto err_common; - - exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs, - ARRAY_SIZE(exynos4_clk_pll_regs)); - if (!exynos4_save_pll) - goto err_soc; - - register_syscore_ops(&exynos4_clk_syscore_ops); - return; - -err_soc: - kfree(exynos4_save_soc); -err_common: - kfree(exynos4_save_common); -err_warn: - pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", - __func__); -} -#else -static void __init exynos4_clk_sleep_init(void) {} -#endif - /* list of all parent clock list */ PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; @@ -1532,7 +1405,17 @@ static void __init exynos4_clk_init(struct device_node *np, if (soc == EXYNOS4X12) exynos4x12_core_down_clock(); - exynos4_clk_sleep_init(); + + samsung_clk_extended_sleep_init(reg_base, + exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), + src_mask_suspend, ARRAY_SIZE(src_mask_suspend)); + if (exynos4_soc == EXYNOS4210) + samsung_clk_extended_sleep_init(reg_base, + exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save), + src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210)); + else + samsung_clk_sleep_init(reg_base, exynos4x12_clk_save, + ARRAY_SIZE(exynos4x12_clk_save)); samsung_clk_of_add_provider(np, ctx);