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Wed, 29 Aug 2018 16:00:24 +0000 (GMT) X-AuditID: cbfec7f2-5e3ff70000001159-57-5b86c318dca6 Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 9E.E7.04284.813C68B5; Wed, 29 Aug 2018 17:00:24 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PE8003XYCGI4J70@eusync1.samsung.com>; Wed, 29 Aug 2018 17:00:24 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 2/2] clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs Date: Wed, 29 Aug 2018 18:00:13 +0200 Message-id: <20180829160013.9447-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-reply-to: <20180829160013.9447-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPIsWRmVeSWpSXmKPExsWy7djPc7qSh9uiDdZ4WGycsZ7V4vqX56wW 589vYLf42HOP1WLG+X1MFmuP3GW3aH/6ktmB3WPTqk42j74tqxg9Pm+SC2CO4rJJSc3JLEst 0rdL4Mq4fPkte8EWiYrJj/azNTAuF+li5OSQEDCRuLj7B1sXIxeHkMAKRolZ354ygiSEBD4z Slx8bwJTNHFbMxtEfBmjxOyraRANDUwSd7pfgjWwCRhKdL3tAisSEXCQ+PzpNSNIEbPAY0aJ rSe/MoMkhAViJdZcb2cCsVkEVCV2ti8Fs3kFbCSud/1jh9gmL7F6wwGwek4BW4mrTcuYQAZJ CHxllXjZ9JwJoshF4vi0x4wQtrDEq+NboJplJDo7DkI1NDNKtM+YxQ7h9ACdMWcHG0SVtcTh 4xdZQWxmAT6JSdumA63jAIrzSnS0CUGUeEi8bnzBAvHnBEaJx+f3sE9glFzAyLCKUTy1tDg3 PbXYMC+1XK84Mbe4NC9dLzk/dxMjMNpO/zv+aQfj10tJhxgFOBiVeHg1ZrdFC7EmlhVX5h5i lOBgVhLh3bsQKMSbklhZlVqUH19UmpNafIhRmoNFSZyXTystWkggPbEkNTs1tSC1CCbLxMEp 1cA4O8DjlsGCroVv9ry5tOHJ9kDDreequWzd3NtmeLXcyBbNejnvRZWbYJXmixuvDJwcQ3Zy me3cHaphqlJz9kbbwW4mts0Llv76f+ynT1Lj7rAD7/VmCqbeiboRl3LnzcmEO/Pz5iz8eW3O 4SU1Wz6tMU2OdnR5F5G7PNwwwuHq92frru48ZCusr8RSnJFoqMVcVJwIAKXI1z6yAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHJMWRmVeSWpSXmKPExsVy+t/xy7oSh9uiDa5tlbTYOGM9q8X1L89Z Lc6f38Bu8bHnHqvFjPP7mCzWHrnLbtH+9CWzA7vHplWdbB59W1YxenzeJBfAHMVlk5Kak1mW WqRvl8CVcfnyW/aCLRIVkx/tZ2tgXC7SxcjJISFgIjFxWzNbFyMXh5DAEkaJl88esUI4TUwS U5bsYAapYhMwlOh628UGYosIOEh8/vSaEaSIWeAxo8S5xRtYQRLCArESa663M4HYLAKqEjvb l4LZvAI2Ete7/rFDrJOXWL3hANhQTgFbiatNy8BqhIBqTk47zTyBkWcBI8MqRpHU0uLc9Nxi Q73ixNzi0rx0veT83E2MwFDZduzn5h2MlzYGH2IU4GBU4uG9MKMtWog1say4MvcQowQHs5II 796FQCHelMTKqtSi/Pii0pzU4kOM0hwsSuK85w0qo4QE0hNLUrNTUwtSi2CyTBycUg2MOsrs y1P5/0S0Z298KDL7b3RvyKRzkUYOVx3Kom7cSvDZxf3fNkpve0nl3pPMCWtSRPIOZWV9/F2d /HC21Z0jjoY6S3T3mG5M/l0s2dcl1/2g6HFpWc2lXxaJn4+XRYUlt+msmya/J+H6T9V3n5Pb +/p58yun6aVOXyvqxWdxg6nVWj3nXIASS3FGoqEWc1FxIgDqlibZEQIAAA== X-CMS-MailID: 20180829160024eucas1p19b9912baece05c529f6bcf64b986bba9 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180829160024eucas1p19b9912baece05c529f6bcf64b986bba9 References: <20180829160013.9447-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Before entering system suspend, one has to ensure that all TOP ACLK clocks are enabled, so do this by storing 0x67ECFFED value to ENABLE_ACLK_TOP register. In case of PERIC CMU, keep all UART PCLK and SCLK clocks as well as all GPIO PCLK clocks enabled. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5433.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.17.1 Reviewed-by: Krzysztof Kozlowski diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 426980514e67..d34e645aba49 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -177,6 +177,12 @@ static const unsigned long top_clk_regs[] __initconst = { ENABLE_CMU_TOP_DIV_STAT, }; +static const struct samsung_clk_reg_dump top_suspend_regs[] = { + { ENABLE_ACLK_TOP, 0x67ECFFED }, /* all clocks enabled */ + { ISP_PLL_CON0, 0x85CC0502 }, /* reset value + ENABLE bit */ + { AUD_PLL_CON0, 0x84830202 }, /* reset value + ENABLE bit */ +}; + /* list of all parent clock list */ PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; @@ -792,6 +798,8 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { .nr_clk_ids = TOP_NR_CLK, .clk_regs = top_clk_regs, .nr_clk_regs = ARRAY_SIZE(top_clk_regs), + .suspend_regs = top_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(top_suspend_regs), }; static void __init exynos5433_cmu_top_init(struct device_node *np) @@ -822,6 +830,11 @@ static const unsigned long cpif_clk_regs[] __initconst = { ENABLE_SCLK_CPIF, }; +static const struct samsung_clk_reg_dump cpif_suspend_regs[] = { + { ENABLE_SCLK_CPIF, 0x3FF }, /* all clocks enabled */ + { MPHY_PLL_CON0, 0x81C70601 }, /* reset value + ENABLE bit */ +}; + /* list of all parent clock list */ PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; @@ -862,6 +875,8 @@ static const struct samsung_cmu_info cpif_cmu_info __initconst = { .nr_clk_ids = CPIF_NR_CLK, .clk_regs = cpif_clk_regs, .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), + .suspend_regs = cpif_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs), }; static void __init exynos5433_cmu_cpif_init(struct device_node *np) @@ -1547,6 +1562,11 @@ static const unsigned long peric_clk_regs[] __initconst = { ENABLE_IP_PERIC2, }; +static const struct samsung_clk_reg_dump peric_suspend_regs[] = { + { ENABLE_PCLK_PERIC0, 0xE00FF000 }, + { ENABLE_SCLK_PERIC, 0x7 }, +}; + static const struct samsung_div_clock peric_div_clks[] __initconst = { /* DIV_PERIC */ DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), @@ -1705,6 +1725,8 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = { .nr_clk_ids = PERIC_NR_CLK, .clk_regs = peric_clk_regs, .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), + .suspend_regs = peric_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs), }; static void __init exynos5433_cmu_peric_init(struct device_node *np)