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Thu, 7 Jun 2018 12:06:23 +0100 (BST) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20180607110622eucas1p26a84fda8d91f2756ff9a371d918afcdb~13AmsUBd71393813938eucas1p25; Thu, 7 Jun 2018 11:06:22 +0000 (GMT) X-AuditID: cbfec7f5-b45ff700000028a9-85-5b1911af10de Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 2B.AD.04178.EA1191B5; Thu, 7 Jun 2018 12:06:22 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P9Y0097E9IGLAA0@eusync1.samsung.com>; Thu, 07 Jun 2018 12:06:22 +0100 (BST) From: Marek Szyprowski To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Inki Dae , Seung-Woo Kim , Bartlomiej Zolnierkiewicz , Andrzej Pietrasiewicz Subject: [PATCH 8/9] drm/exynos: gsc: Fix support for NV16/61, YUV420/YVU420 and YUV422 modes Date: Thu, 07 Jun 2018 13:06:13 +0200 Message-id: <20180607110614.335-9-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-reply-to: <20180607110614.335-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIIsWRmVeSWpSXmKPExsWy7djP87rrBSWjDc4v4LWY9bKdxWLjjPWs Fle+vmezmHR/AovFjPP7mCzWHrnLbjFj8ks2B3aP+93HmTz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoEr4+fNdpaCN+IVHSv2szQw3hTuYuTkkBAwkVg37xZzFyMXh5DACkaJw41f2EESQgKf GSV+vGaDKbq+ej0jRNEyRokJKyayQTgNTBKb5n5lAqliEzCU6HrbBdYhIuAm0XR4JitIEbPA Y0aJtbs3g40VFoiX6F9/C6yBRUBV4sK7r2BxXgFriWeLV7FDrJOXWL3hADOIzSlgI3F+2SYm kEESAj9ZJW59v8wMUeQi8XDRN0YIW1ji1fEtUM0yEp0dB6Eamhkl2mfMYodwehglts7ZAfWR tcTh4xdZQWxmAT6JSdumA03lAIrzSnS0CUGUeEicPjGPFeLPfkaJc4cWsU9glFzAyLCKUTy1 tDg3PbXYOC+1XK84Mbe4NC9dLzk/dxMjMOJO/zv+dQfjvj9JhxgFOBiVeHgb7otHC7EmlhVX 5h5ilOBgVhLhTbwkFi3Em5JYWZValB9fVJqTWnyIUZqDRUmcN06jLkpIID2xJDU7NbUgtQgm y8TBKdXAaMkuWPzQp8OBO2S5XM+Ud44rj9p8UXg732TzxSKHc2+vuf06t1Jb79xF7Xj25LxD HDu21bzm3v1tg4be3pXLr62MTJt3aOGqnrU/tguyWfdviZ0npLK0d025p4VKqNZHnn/HLCK3 H5jWfH3egeOb9yw1t2SZNEF7flnxdo1E3jVae2eqt9mGJimxFGckGmoxFxUnAgAj6f8QtAIA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHJMWRmVeSWpSXmKPExsVy+t/xy7rrBCWjDXZtU7eY9bKdxWLjjPWs Fle+vmezmHR/AovFjPP7mCzWHrnLbjFj8ks2B3aP+93HmTz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoEr4+fNdpaCN+IVHSv2szQw3hTuYuTkkBAwkbi+ej1jFyMXh5DAEkaJ5j/7WCCcJiaJ Fws+soNUsQkYSnS97WIDsUUE3CSaDs9kBSliFnjMKPFx2ylWkISwQLzE+u+fwRpYBFQlLrz7 CmbzClhLPFu8ih1inbzE6g0HmEFsTgEbifPLNjGB2EJANW8fnGafwMizgJFhFaNIamlxbnpu saFecWJucWleul5yfu4mRmCobDv2c/MOxksbgw8xCnAwKvHwNtwXjxZiTSwrrsw9xCjBwawk wpt4SSxaiDclsbIqtSg/vqg0J7X4EKM0B4uSOO95g8ooIYH0xJLU7NTUgtQimCwTB6dUA2Pk TIupPZufxvCwL9q5PiZ+q+2vW3OT+cWqlpwLybk6vbpMaXHnppP7ekoYry60dlwf4Wsk/MLr WLe8RoXLTdkr0aturDxS178vx80xxjW+Vehz+I7YuZ9zJbbssg962pwm16fx6OJds63uJVrZ e+90/jJ/PNX36P9zh2dvO75u1zU+NuWzPVpKLMUZiYZazEXFiQBaJ1h1EQIAAA== X-CMS-MailID: 20180607110622eucas1p26a84fda8d91f2756ff9a371d918afcdb X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180607110622eucas1p26a84fda8d91f2756ff9a371d918afcdb References: <20180607110614.335-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Fix following issues related to planar YUV pixel format configuration: - NV16/61 modes were incorrectly programmed as NV12/21, - YVU420 was programmed as YUV420 on source, - YVU420 and YUV422 were programmed as YUV420 on output. Signed-off-by: Marek Szyprowski --- drivers/gpu/drm/exynos/exynos_drm_gsc.c | 29 +++++++++++++++++-------- drivers/gpu/drm/exynos/regs-gsc.h | 1 + 2 files changed, 21 insertions(+), 9 deletions(-) -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c index 97182dadad72..bf1320ea3712 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c @@ -492,21 +492,25 @@ static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt) GSC_IN_CHROMA_ORDER_CRCB); break; case DRM_FORMAT_NV21: + cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P); + break; case DRM_FORMAT_NV61: - cfg |= (GSC_IN_CHROMA_ORDER_CRCB | - GSC_IN_YUV420_2P); + cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P); break; case DRM_FORMAT_YUV422: cfg |= GSC_IN_YUV422_3P; break; case DRM_FORMAT_YUV420: + cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P); + break; case DRM_FORMAT_YVU420: - cfg |= GSC_IN_YUV420_3P; + cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P); break; case DRM_FORMAT_NV12: + cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P); + break; case DRM_FORMAT_NV16: - cfg |= (GSC_IN_CHROMA_ORDER_CBCR | - GSC_IN_YUV420_2P); + cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P); break; } @@ -672,18 +676,25 @@ static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt) GSC_OUT_CHROMA_ORDER_CRCB); break; case DRM_FORMAT_NV21: - case DRM_FORMAT_NV61: cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P); break; + case DRM_FORMAT_NV61: + cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P); + break; case DRM_FORMAT_YUV422: + cfg |= GSC_OUT_YUV422_3P; + break; case DRM_FORMAT_YUV420: + cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P); + break; case DRM_FORMAT_YVU420: - cfg |= GSC_OUT_YUV420_3P; + cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P); break; case DRM_FORMAT_NV12: + cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P); + break; case DRM_FORMAT_NV16: - cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | - GSC_OUT_YUV420_2P); + cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P); break; } diff --git a/drivers/gpu/drm/exynos/regs-gsc.h b/drivers/gpu/drm/exynos/regs-gsc.h index 4704a993cbb7..16b39734115c 100644 --- a/drivers/gpu/drm/exynos/regs-gsc.h +++ b/drivers/gpu/drm/exynos/regs-gsc.h @@ -138,6 +138,7 @@ #define GSC_OUT_YUV420_3P (3 << 4) #define GSC_OUT_YUV422_1P (4 << 4) #define GSC_OUT_YUV422_2P (5 << 4) +#define GSC_OUT_YUV422_3P (6 << 4) #define GSC_OUT_YUV444 (7 << 4) #define GSC_OUT_TILE_TYPE_MASK (1 << 2) #define GSC_OUT_TILE_C_16x8 (0 << 2)